Manual Switch — Control Systems/Signal Routing
Control_Systems/Signal_Routing/Manual_Switch · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Manual Switch
Control Systems / Signal Routing
Passes one of its two inputs straight through, chosen by a setting rather than by a signal: y = u1 or y = u2. The choice is part of the model, so it is the same on every sample of the run and the input that is not selected is not read at all.
Ports
- u1 – the first input, of any size [m,n]. It becomes the output when Switch Position is Input 1.
- u2 – the second input. It must be the SAME size [m,n] as u1, because either may become the output; a mismatch is reported rather than broadcast or trimmed.
- Output – y, the selected input unchanged, of that same size [m,n].
Parameters
- Switch Position – which input reaches the output. This selects
the branch rather than retuning it, so each option is a separate code path.
- Input 1 – the first port, the default.
- Input 2 – the second port.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. The position is not a tunable parameter on
the exported core: it is resolved at export time, so the generated body is a
plain copy of the selected input and the other input does not appear in it. Re-
export after moving the switch. The three HDL targets are fully synthesizable
– a copy needs no arithmetic, so nothing is evaluated in
real.
Simulink bridge
Import and export, mapped to simulink/Signal Routing/Manual Switch.
"Switch Position" to sw, with Input 1 written as
1 and Input 2 as 0 – that is Simulink's
own numbering, measured against R2026a, and it is the opposite of what the
values suggest. The mapping is one option for one option, so the round trip is
lossless. varsize is always written as off: every
ICore signal has one fixed size, so there is no variable-size mode to offer and
pinning it keeps the two sides comparing the same thing. "Sampling Time (s)" to
SampleTime, as on every block.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear in the reduction sense – the block has two inputs, so it is not SISO and model reduction refuses it. It deliberately carries no state space: one naming only the selected input would quietly discard the other path.
- To switch on a SIGNAL rather than a setting, use Signal Routing / Switch; to choose among more than two inputs, use Signal Routing / Multiport Switch.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Routing/Manual_Switch |
| family | Control_Systems/Signal_Routing |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Manual_Switch |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Manual_Switch/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Manual_Switch.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Manual_Switch/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Manual_Switch.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u1 |
| 2 | in | ICoreDouble | u2 |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Switch Position | Input 1%~%Input 2~~Input 1 | sw |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Routing/Manual Switch |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | varsize = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Switch Position | sw | Input 1 → 1, Input 2 → 0 |
Caveat (shown to the user): the Simulink parameter is
sw, and it numbers the FIRST input 1 and the second 0 -- measured, and the opposite of what the names suggest; the variable-size mode is pinned off because every ICore signal has one fixed size
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Manual Switch block -- one of two inputs, chosen by a setting rather than by a signal y = u1 or y = u2, decided by "Switch Position" and fixed for the whole run. There is no control port: the choice belongs to the model, so it is resolved at EXPORT time and the generated core carries the selected branch alone -- no comparison, no second read, and in the three HDL targets no extra logic. Signal_Routing/Switch is the block whose choice arrives on a wire and therefore has to carry both paths.
Both inputs must be the same size, since either may become the output.
⚠ THE SIMULINK PARAMETER READS BACKWARDS AND THAT IS MEASURED, NOT GUESSED.
swis 1 for the FIRST input and 0 for the second (R2026a, two distinguishable constants on the two ports), so the catalog's enum table maps "Input 1" -> "1" and "Input 2" -> "0". Reading it the other way round is a silent inversion: nothing errors, the model simply routes the other signal.
varsizeis pinned off. Simulink offers a variable-size mode on this block; every ICore signal has one fixed size, so there is no choice to carry and pinning it is what keeps the two sides comparing the same thing.Algebraic and stateless. No state space -- see the header.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.