Data Store Read — Control Systems/Signal Routing
Control_Systems/Signal_Routing/Data_Store_Read · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Data Store Read
Control Systems / Signal Routing
Outputs the current value of the data store it names: y = the store,
with no wire to the Data Store Write that last wrote it. Before any Write it
gives the store’s initial value. Simulink’s Data Store Read
(BlockType=DataStoreRead).
Ports
- Output – y, the store’s value, the size of the store (its Data Store Memory’s initial value, expanded by its Dimensions).
Parameters
- Data store name –
A(default). The store to read: the Data Store Memory of that name at this block’s level or the nearest level above it. Case-sensitive, and never looked up in the variables space. A name no Memory declares on that path stops the run in Simulink’s words (DSMemoryBlockNotFound). - Sampling Time (s) – zero or less inherits the solver’s rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog,
SystemVerilog and PLC Structured Text copy the store, the exported core’s
named global (ds0, …), into the output, element by element.
An export that does not hold the store – a subsystem exported alone while
its Memory sits outside it – is refused by name.
Simulink bridge
Both directions, as simulink/Signal Routing/Data Store Read.
Data store name goes to DataStoreName; "Sampling Time
(s)" goes to SampleTime, as on every block. Simulink’s
element selection (DataStoreElements, EnableIndexing)
does not cross: a Read here gives the whole store.
Notes
- A Read runs after the Writes of its store in the same step wherever no data path says otherwise, so it gives what they wrote this step. When its own output reaches a Write of the same store (Read → +1 → Write), the data path wins and it gives last step’s value: a counter with no delay block, as in Simulink.
- It reads once per step, never at a continuous solver’s intermediate stages, and holds its output in between. Its Memory’s Read before write diagnostic is checked on each read.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Routing/Data_Store_Read |
| family | Control_Systems/Signal_Routing |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Data_Store_Read |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Data_Store_Read/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Data_Store_Read.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Data_Store_Read/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Data_Store_Read.h |
| default size on canvas | 80 × 60 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Data store name | A | DataStoreName |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Routing/Data Store Read |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Data store name | DataStoreName | passes through |
Caveat (shown to the user): The whole store crosses: Simulink's element selection (DataStoreElements, EnableIndexing) does not.
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.