Bus Creator — Control Systems/Signal Routing

Bus Creator

Control Systems / Signal Routing

Packs several signals into one bus: a single wire carrying named elements, so a group of related signals can be routed together and taken apart again by a Bus Selector at the far end.

Ports

• Inputs – two by default, and the count is user-editable. Each one becomes one element of the bus, in port order. An input accepts any signal type except another bus, and the element takes whatever that input carries – its type and its size are copied, not chosen here.
• Output (bus) – the bus. Its "size" is the list of elements rather than a number of rows and columns, which is why the block face shows the element count.

Parameters

• Element names – a comma-separated list, one name per input, in port order. These are what a Bus Selector picks by, so they must be unique and none may be blank. Adding an input without adding a name is an error the build reports.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Notes

• Routing only – no value is scaled, converted or reordered. What arrives on input n is what element n carries.
• A bus cannot contain another bus. Connecting one to an input is refused with the element's name, rather than silently flattened.
• Algebraic, with no state, and no state space: there is no A/B/C/D that describes packing differently typed signals into one.
• The element types are decided by what you connect, so changing an upstream block's output type changes the bus. Both ends are checked when the model is built: two bus wires fit together only if their elements match in order, name, type and size.

Code export

Exported to Python (a dict) and MATLAB (a struct), keyed by the element names above – so the generated code selects an element by the same name the Bus Selector does.

Exported to C, C++, Java and Rust as a declared record: a struct (a static class in Java) named Bus0, Bus1, and so on, one per distinct bus in the model, with one field per element under the element's own name. Two buses with the same elements, in the same order, of the same types and sizes, share one record. Each field is stored the way a signal of that type and size is stored in that language: a matrix of doubles for a numeric element, text for a String. Because each element name becomes a field, it must be a plain identifier (a letter or underscore, then letters, digits or underscores) and not a reserved word of C, C++, Java or Rust; export to those four refuses any other name and says which one. Simulink sets the same rule for bus element names.

Not exported to VHDL, Verilog, SystemVerilog or PLC Structured Text. Each refuses by name at export, with its own reason: the HDL trio needs a fixed bit width, and the Structured Text exporter emits no type declarations at all. Select the elements you need with a Bus Selector and route them separately if the model has to generate code for one of those.

Simulink bridge

Import and export, mapped to simulink/Signal Routing/Bus Creator. The port count crosses as Inputs. "Sampling Time (s)" does not cross. Simulink's Bus Creator is a virtual block with no SampleTime parameter at all, so an explicit rate here is reported as staying on the ICore side, in the export report and as a warning in the generated script.

The element names cross as the names of the input lines. Simulink has no element-name setting: it names each element after the line into its port, and signal1, signal2, and so on for an unnamed line. So an export names each input line after its element, and a Bus Selector in Simulink then finds the element by the same name. On import, a Simulink Bus Creator that a Bus Selector reads becomes this block, its elements named after its input lines, or signalK where a line has no name. A Bus Creator that only feeds blocks reading it as a vector becomes a Mux, because that is what Simulink computes there. One source line can carry only one name, so a signal feeding two bus elements of different names keeps the first, and the export says so.