Bus Assignment — Control Systems/Signal Routing

Control_Systems/Signal_Routing/Bus_Assignment · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Bus Assignment

Control Systems / Signal Routing

Replaces chosen elements of a bundle in place and passes the rest through:

y = u₀, with element a_k's rows overwritten by input port k+1, where Element Widths gives each element's row count and Assigned Elements names the elements in the order the value ports appear.

The output keeps the bundle's order, not the assignment list's: assigning element 3 then element 1 still answers a bundle in element order, with both replaced. The list orders the PORTS.

Ports

Bundle (input 1) – the stacked signal u₀ to modify, any size [m,n]. Elements are rows, and the declared widths must add up to m.
Values (inputs 2…) – one per assigned element, in Assigned Elements order. Each must be exactly its element's size – w(a_k) rows and the bundle's own column count. A mismatch stops the run; there is no broadcasting, which is Simulink's behaviour too. The input port count is user-editable on the canvas and must be one more than the number of assigned elements.
Output – y, always the size of the bundle input.

Parameters

Element Widths – the row count of each element of the incoming bundle, as a list: [1 2 1 1] describes a five-row bundle of four elements, the second of which is two rows. Each entry must be a whole number of at least 1, and the sum must equal the bundle's row count – checked, not assumed. The default [1 1] describes two scalars.
Assigned Elements – which elements the value ports replace, counting elements from 1, in port order. [3 1] means the second input port replaces element 3 and the third replaces element 1. The list length must be one less than the input port count. An element named twice is written twice and the last write wins.
Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every one emits the same plan – copy the bundle, then overwrite the assigned rows – with the offsets and widths resolved at export time, so nothing computes an index at run time and nothing is exposed as a tunable parameter. The three HDL targets are therefore genuinely synthesizable: there is no arithmetic to quantize, only wiring.

Simulink bridge

No Simulink equivalent, and the reason is a missing TYPE rather than a gap in this block – the same one Bus Selector gives. Simulink's Bus Assignment names the elements it replaces (AssignedSignals) because a Simulink bus is a labelled structure; ICore has no bus type, a bundle of signals being a stacked column, and a column has positions rather than names. A name cannot be turned into a position without knowing the bus's structure, so the bridge reports this block rather than asserting a mapping that would be wrong for every bus whose elements were ever named.

Moving a model by hand: write the bus's element widths into Element Widths in bus order and translate the assigned names to their positions. What is lost is the labels, not the values or their order.

Measured in R2026a: over a bus of (1, 2, 3) with AssignedSignals = signal3,signal1 and 88 and 99 on the two value ports, Simulink answers [99 2 88] – which is what this block reproduces by number – and assigning a scalar to a two-row element is refused outright rather than broadcast.

Notes

Algebraic, with no state: the output is built from this instant's inputs.
An element the list does not name is copied through untouched, so the block is a pass-through for everything it was not asked to replace.
Base_Blocks/Assignment does the same arithmetic by linear index and takes all its replacement values on one port, packed in index order. Reach for that one when the positions are what you have; reach for this one when a port per element is what lines up with the model.
Widths that do not add up to the bundle, an element that does not exist, a list whose length disagrees with the port count, and a value port of the wrong height each stop the run and name the block.
Deliberately carries no state space: the block is routing rather than a linear system, and it is not the one-in-one-out shape model reduction merges.

Code facts#

Fact	Value
registered type	`Control_Systems/Signal_Routing/Bus_Assignment`
family	`Control_Systems/Signal_Routing`
solver environment class	`ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Bus_Assignment`
source	`src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Bus_Assignment/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Bus_Assignment.cpp`
header	`src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Bus_Assignment/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Bus_Assignment.h`
default size on canvas	90 × 80 px
ports at insert	2 in, 1 out
code generators implemented	`Python`, `MATLAB`, `Java`, `Rust`, `C`, `C++`, `VHDL`, `Verilog`, `SystemVerilog`, `PLC Structured Text`

Ports#

#	Direction	Signal type	Description label
1	in	`ICoreDouble`	bundle
2	in	`ICoreDouble`	value
3	out	`ICoreDouble`	—

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variable	Default	Simulink parameter
`Element Widths`	`[1 1]`	—
`Assigned Elements`	`[1]`	—

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

Simulink bridge#


support	`Support::None`
Simulink path	—
port-count rule	`PortsParam::None`
`SampleTime` parameter	yes

Caveat (shown to the user): Simulink's Bus Assignment names the elements it replaces (AssignedSignals) because a Simulink bus is a labelled structure. ICore has no bus type at all: a bundle of signals is a stacked column, which is what Mux builds, and a column has positions rather than names -- so this block assigns by NUMBER and there is no lossless mapping either way. The bridge reports it rather than asserting one that would be wrong for every bus whose elements were ever named, which is Bus Selector's call and In Bus Element's before it. Moving a model by hand: write the bus's element widths into "Element Widths" in bus order and translate the assigned names to their positions; what is lost is the labels, not the values or their order. Note that Base_Blocks/Assignment does the same arithmetic by LINEAR INDEX with all the replacement values on one port -- it is the block to reach for when positions are what you have

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:

B0 every stimulus in the sample errored — cross-checks skipped

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Bus Assignment -- replace named elements of a bundle IN PLACE y = u0, with element a_k's rows overwritten by input port k+1, where "Element Widths" gives each element's row count and "Assigned Elements" gives the element numbers a in the order the value ports appear. 1 + N inputs, one output the size of the first input.

MEASURED in R2026a before any of this was written, and two of the three findings decide the block:

THE OUTPUT KEEPS THE BUNDLE'S ORDER, NOT THE ASSIGNMENT LIST'S. Over a bus of (1, 2, 3)

with AssignedSignals = signal3,signal1 and 88 on the first value port, 99 on the second, Simulink answers [99 2 88]. The list orders the PORTS; the result stays in element order.

THE PORT COUNT FOLLOWS THE LIST: one entry gives 2 inputs, two entries give 3.
WIDTHS MUST MATCH EXACTLY -- assigning a scalar to a two-row element is a hard error

("Incoming buses to block ... have a dimension mismatch"), not a broadcast.

NO SIMULINK BRIDGE, for Bus Selector's reason: Simulink names bus elements because a bus is a labelled structure, and a stacked column has positions rather than names.

NOT A DUPLICATE OF Base_Blocks/Assignment, though the arithmetic is the same one: that block takes every replacement value on ONE port packed in index order, this one takes a port per element, which is what makes the ports line up with a bus's structure.

Ten backends emit the same plan -- copy the bundle, overwrite the assigned rows -- with the offsets and widths resolved here, so the three HDL targets are wiring.

Algebraic and stateless. No state space -- see the header.

Sample results#

No stimulus produced a sampled output in this rig — Bus assignment's declared element widths do not add up to its bundle at: ICore Blocks/Home/Bus Assignment. That is a fact about the single-block rig, not a verdict on the block: an offline batch fit, a block whose output only appears at onSolverFinish, or one that needs a driven environment cannot be exercised alone.

Category unsampled · sample time 0.1 · 60 steps · commit 0c70b2f26f3a47f81851de7f57aa2aa4ffdc8a9d · produced by docsSample --out <folder> --blocks Bus_Selector Bus_Assignment --steps 60

Sample data: docs/generated/samples/Control_Systems__Signal_Routing__Bus_Assignment.json