Prony Design — Control Systems/Signal Modeling
Control_Systems/Signal_Modeling/Prony_Design · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Prony Design
Control Systems / Signal Modeling
Fits an IIR model b(z)/a(z) of numerator order nb and denominator
order na to the frame on its input, read as an impulse response –
MATLAB's prony(h, nb, na). With the frame normalized by its first
sample (h(1), or 1 when that is zero) and H its lower-triangular Toeplitz
matrix, the denominator comes from the equations past sample nb:
a = [1; −x], x the least-squares solution of H(nb+2:L, 2:na+1)·x = H(nb+2:L, 1)
and the numerator matches the first nb+1 samples exactly: b(m) = h(1)·Σj≤m a(j)·hn(m−j).
Ports
- h – the frame to fit, an [L,1] column with the oldest sample first, as MATLAB takes its vector: the impulse response h(1) … h(L). L is read off the wire and must be at least nb + na + 2 and at most 64. A Tapped Delay with Delay Order Oldest turns a stream into such a frame.
- b – the numerator coefficients, [nb+1, 1], in descending powers of z−1.
- a – the denominator coefficients, [na+1, 1], with a(1) = 1.
Parameters
- Numerator Order – nb, 0 to 8.
- Denominator Order – na, 1 to 8.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, all from one program, so every target does the same arithmetic in the same order as the simulation. The orders and the frame length are structural; re-export after changing them.
The three HDL targets run the fit in real arithmetic and
quantize only at the ports: simulation-only, not offered as
synthesizable. A least-squares solve has a division by a pivot and a data-dependent
row exchange, neither of which belongs in a Q16.16 datapath.
Simulink bridge
None (Support::None). prony is a Signal
Processing Toolbox function and that toolbox ships no Simulink library, so
there is no path a diagram could name. The bridge reports this block rather than
dropping it silently, and it has no parity testbench; code export
verification covers all ten languages.
Notes
- Verified against R2026a: see the source banner for the frame and the
measured agreement with
prony. - ⚠ The least-squares step is solved through the normal equations by Gaussian elimination with partial pivoting, where MATLAB's backslash uses a QR factorization. Both give the least-squares answer; they differ by rounding, which grows with how ill-conditioned the frame is. The measured gap on the banner is for a well-posed frame.
- A frame that does not determine the model – a constant, or all zeros – makes the elimination divide by zero, and the outputs are NaN for that frame, as MATLAB's backslash would warn and answer Inf or NaN too.
- Algebraic: every output depends on this frame alone. It is a fit, not a filter, so it carries no state space.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Modeling/Prony_Design |
| family | Control_Systems/Signal_Modeling |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Prony_Design |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/Prony_Design/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Prony_Design.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/Prony_Design/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Prony_Design.h |
| default size on canvas | 150 × 80 px |
| ports at insert | 1 in, 2 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | h |
| 2 | out | ICoreDouble | b |
| 3 | out | ICoreDouble | a |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Numerator Order | 2 | — |
Denominator Order | 2 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): prony is a Signal Processing Toolbox function, not a Simulink library block -- that toolbox ships no Simulink library at all -- so there is no path a diagram could name; the block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Prony Design -- MATLAB's prony, an IIR model from a frame c = h(1) (1 when it is zero), hn = h / c, H = lower-triangular Toeplitz of hn a = [1; -x], x = the least-squares solution of H(nb+2:L, 2:na+1) * x = H(nb+2:L, 1) b(m) = c * SUM(j <= m) a(j) * hn(m - j), m = 0 .. nb
Read out of the installed prony.m (R2026a), step for step: the normalization by h(1), the guard that replaces a zero h(1) by 1, and b = c*a*H1.' are MATLAB's. The one departure is the least-squares SOLVE -- normal equations with partial pivoting here, QR in MATLAB's backslash; see ICorePronySupport.cpp.
Measured against R2026a on the export-verify rig's own frames h0 + w*u, u = -1 .. 1 in 41 steps, where h0 = filter([0.8 -0.3 0.15], [1 -1.1 0.55 -0.12], impulse) + 0.01*sin(1:16): the EXPORTED Python core agrees with prony(h, 3, 4) to 4.2e-12 on every frame.
Support::None: prony is a Signal Processing Toolbox function and that toolbox ships no Simulink library.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.