LSF LSP To LPC — Control Systems/Signal Modeling
Control_Systems/Signal_Modeling/LSF_LSP_To_LPC · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
LSF/LSP to LPC
Control Systems / Signal Modeling
Rebuilds the LPC vector A = [1 a1 … ap] from p line spectral frequencies (or their cosines, the line spectral pairs): the odd-numbered frequencies are the roots of Q(z) and the even-numbered ones of P(z), each conjugate pair a real quadratic [1, −2cosω, 1]; Q and P are closed by (1 + z−1) and (1 − z−1) for an even order, by (1 − z−2) on P alone for an odd one, and A = (P + Q)/2 without its last term. This is MATLAB's lsf2poly.
Ports
- u – the p frequencies or pairs, [p,1], in the unit Input names.
- A – the LPC vector, [p+1,1], starting at 1.
Parameters
- Input – the unit of u:
- LSP in range (-1 1) (the default, as Simulink's) – cosω itself.
- LSF normalized in range (0 0.5) – ω/2π.
- LSF in range (0 pi) – ω in radians.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The input length and the conversion are baked into the core at export time.
The three HDL targets are simulation-only: they carry the arithmetic in real and quantize only at the port boundary. The LSF inputs pass through a cosine, which the Q16.16 packages do not carry. The cores simulate correctly and are not offered as synthesizable.
Simulink bridge
Import and export, mapped to dsplp/LSF//LSP to LPC Conversion – the DSP System Toolbox block (a doubled // is how Simulink writes a slash INSIDE a block name, and the library breaks this block's name over two lines). "Input" to input (one to one, every option).
"Sampling Time (s)" does not cross. dsplp/LSF//LSP to LPC Conversion defines no SampleTime parameter – verified against the R2026a block dialog – and set_param on a parameter a block does not define is a hard error that aborts the whole generated script.
Notes
- Stateless and algebraic.
- Nothing is refused: out-of-range or unordered frequencies still give a polynomial, exactly as the Simulink block does (measured: LSF −0.3 and 4.0 were accepted, and this formula reproduced the answer). MATLAB's
lsf2polyerrors on them. - The inverse, LPC to LSF/LSP Conversion, is not in this library yet: its root search (a 64-step grid plus four bisections) lands 1e-6 away from
poly2lsf, and matching it is a separate piece of work.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Modeling/LSF_LSP_To_LPC |
| family | Control_Systems/Signal_Modeling |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LSF_LSP_To_LPC |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/LSF_LSP_To_LPC/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LSF_LSP_To_LPC.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/LSF_LSP_To_LPC/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LSF_LSP_To_LPC.h |
| default size on canvas | 120 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | A |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Input | LSP in range (-1 1)%~%LSF normalized in range (0 0.5)%~%L… | input |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | dsplp/LSF//LSP to LPC\nConversion |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Input | input | LSP in range (-1 1) → LSP in range (-1 1), LSF normalized in range (0 0.5) → LSF normalized in range (0 0.5), LSF in range (0 pi) → LSF in range (0 pi) |
Caveat (shown to the user): dsplp/LSF//LSP to LPC Conversion has NO SampleTime parameter (verified against the R2026a block dialog), so "Sampling Time (s)" does not cross
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
LSF/LSP to LPC block — dsplp's dsplp/LSF//LSP to LPC Conversion, measured on R2026a before it was written Rebuilds the LPC vector A = [1 a1 ... ap] from p line spectral frequencies (or their cosines, the line spectral pairs): the odd-numbered frequencies are the roots of Q(z) and the even-numbered ones of P(z), each conjugate pair a real quadratic [1, -2cosw, 1]; Q and P are closed by (1 + z^-1) and (1 - z^-1) for an even order, by (1 - z^-2) on P alone for an odd one, and A = (P + Q)/2 without its last term.
The conversions, their measured facts and the ten emitted bodies live in ICoreLpcConversionSupport (the arithmetic) and ICoreStatementProgram (the ten spellings); this file is the block's ports, parameters and Simulink bridge.
Code export: all ten targets. The three HDL ones are SIMULATION-ONLY
realarithmetic.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 [2x1] entry 0 |
|---|---|---|
| 0 | -2 | [1, 2] |
| 0.4 | 0.5 | [1, -0.5] |
| 0.8 | -2 | [1, 2] |
| 1.2 | 0.5 | [1, -0.5] |
| 1.6 | -2 | [1, 2] |
| 2 | 0.5 | [1, -0.5] |
| 2.4 | -2 | [1, 2] |
| 2.8 | 0.5 | [1, -0.5] |
| 3.2 | -2 | [1, 2] |
| 3.6 | 0.5 | [1, -0.5] |
| 4 | -2 | [1, 2] |
| 4.4 | 0.5 | [1, -0.5] |
| 4.8 | -2 | [1, 2] |
| 5.2 | 0.5 | [1, -0.5] |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 1 … 1 |
ramp | Ramp: slope 1 from t = 0 | 1 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 1 … 1 |
step | Step: 0 -> 1 at t = 1 s | 1 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 4bc64690c · produced by docsSample --out <folder> --blocks LPC_To_From_RC LPC_RC_To_Autocorrelation LPC_To_From_Cepstral LSF_LSP_To_LPC --steps 60 · data docs/generated/samples/Control_Systems__Signal_Modeling__LSF_LSP_To_LPC.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).