Width — Control Systems/Signal Attributes
Control_Systems/Signal_Attributes/Width · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Width
Control Systems / Signal Attributes
Reports how many elements its input signal carries: y = m×n for an input of size [m,n], delivered as a 1×1 scalar. It is the whole element count and not a dimension – a [2,3] input answers 6, a three-element vector answers 3, and a scalar answers 1.
Ports
- Input – the signal u whose width is reported, of any size [m,n]. Its VALUES are never read; only its size is.
- Output – y, always 1×1 whatever the input's size. This is the one block in the family whose output size does not follow its input's.
Parameters
- None. The width is a property of the signal that arrives, not something to set: to produce a constant of your own choosing use Constant.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The width is inlined as a literal in every one of them rather than exposed as a tunable parameter, and that is not an optimization: signal sizes are resolved once when the model is built, so on a generated core the width is already fixed and there is nothing left to measure at run time. The three HDL targets are fully synthesizable – the body is one constant assignment, with no arithmetic to quantize.
Simulink bridge
Import and export, mapped to simulink/Signal Attributes/Width. There are
no parameters to map: Simulink's block carries only output-data-type settings
(OutDataTypeMode, DataType), which have no counterpart here because
every ICore signal is a matrix of doubles, so they are left at their Simulink defaults.
The rate does NOT cross. That block defines no SampleTime parameter
– verified by set_param against R2026a, which answers "Width block does not
have a parameter named 'SampleTime'" – so "Sampling Time (s)" stays on the ICore side.
Writing it anyway would be a hard error that aborts the whole generated script rather than a
warning that degrades.
Notes
- Algebraic, with no state, and constant for a whole run: the answer depends on the size of the wire, which the model build resolves before the first step.
- Deliberately carries no state space. The output does not depend on the input at all, so there is no A/B/C/D that represents it – the relation would need a constant term and a state space has nowhere to hold one. Model reduction reports the block as unmergeable rather than absorbing it as a zero gain.
- An input that is left unconnected resolves to [1,1] like any other signal, so the block answers 1 rather than reporting an error.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Attributes/Width |
| family | Control_Systems/Signal_Attributes |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Width |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Width/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Width.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Width/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Width.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Attributes/Width |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the rate does not cross: the Simulink block defines no SampleTime parameter, so "Sampling Time (s)" stays on the ICore side. Simulink's OutDataTypeMode and DataType have no counterpart here, every ICore signal being a matrix of doubles
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Width -- how many elements the input signal carries y = m*n for an input of size [m,n]: the whole ELEMENT COUNT, as a 1x1 scalar. See the header for why that is a count rather than a dimension, and for the measurement behind it.
ONE PLACE COUNTS, TEN BACKENDS INLINE IT. widthOf() reads the input port's resolved size, and compute_h and all ten generators go through it, so the live run and every export cannot disagree about what "width" means. It is a free function in this file rather than a member, because a header here holds public declarations and the two-line private residue and nothing else.
The number is fixed for a whole run: port sizes are resolved by the model build before the first step, so every export writes a literal and no target needs to measure anything at run time. That is also why the block is a legitimate constant on a deployed core.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.