Rate Transition — Control Systems/Signal Attributes

Rate Transition

Control Systems / Signal Attributes

Re-samples a signal onto a slower period and holds it in between. With N = round(Output Sample Time / the block's own period):

y[k] = u[N·floor(k/N)]

So at N = 3 the block takes the input on samples 0, 3, 6, … and repeats each taken value twice. The first sample is taken, not held over, so nothing is delayed at the start, and the value published between takes is the one taken at the top of the interval. N = 1 – which is what a non-positive Output Sample Time means – is a plain wire.

Ports

• Input – the signal u at the fast rate, of any size [m,n]. It is read on every sample and used on one in N.
• Output – y, the same size as the input, updated on one sample in N and holding its value in between. The block never reshapes a signal.

Parameters

• Output Sample Time (s) – the period to re-sample onto, a scalar in seconds. Zero or less means no re-sampling and the block is a wire; that is the default, and matches the −1 the Simulink counterpart ships with. A value that is not a whole multiple of the block's own period is rounded to the nearest multiple and reported once, rather than refused – the ratio, not the period, is what the block can act on.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. This is the fast side: the output period above is counted in multiples of it.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. N is resolved at export time and inlined as a constant rather than exposed as a tunable parameter, because the count is fixed once the model's rates are: retuning it on a deployed core would mean re-deriving it from a period the core no longer carries. At N = 1 the block emits a plain copy with no state at all, so a model that leaves the parameter alone pays nothing for the block being present.

The three HDL targets are synthesizable. The state is one counter register and one held value per element, with no arithmetic to quantize – values are copied, not computed, so the exported core is bit-exact against the simulation rather than merely close.

Simulink bridge

Import and export, mapped to simulink/Signal Attributes/Rate Transition. "Output Sample Time (s)" to OutPortSampleTime, as a plain pass-through; Simulink's OutPortSampleTimeOpt ships as Specify, which is the setting that pair needs, so nothing has to be written to it.

The rate does NOT cross. That block defines no SampleTime parameter – set_param against R2026a answers "RateTransition block does not have a parameter named 'SampleTime'" – so "Sampling Time (s)" stays on the ICore side. Writing it anyway would be a hard error that aborts the whole generated script.

Three Simulink parameters have no counterpart here and are left at their defaults. Integrity and Deterministic were measured to make no difference at all to the fast-to-slow behaviour this block implements – an output period of 0.02 answered [1 1 3 3 5 5 …] with each of them on and off. InitialCondition belongs to the slow-to-fast direction, which is not implemented (see Notes), and never appears in the direction that is.

Notes

• Stateful: a phase counter, plus the value currently being held.
• Discrete only. N counts SAMPLES, which only means what it says if the block is evaluated once per sample; under a continuous solver the sub-steps of a single step would each advance the counter. The block therefore takes its period from its own Sampling Time (s), falling back to the model's global rate.
• Fast to slow only. Simulink's block also converts slow to fast, delaying by a whole input period and filling that period with an initial condition. That direction needs the rate of the signal ARRIVING, and a block here is told its own period and never its input's, so it is not offered rather than approximated.
• Deliberately carries no state space. The block is linear but not time-invariant – which of the N phases a sample falls in decides whether the output follows the input or ignores it – so no single A/B/C/D describes it, and a reduction that absorbed it would silently put the fast rate back.