Data Type Conversion Inherited — Control Systems/Signal Attributes

Data Type Conversion Inherited

Control Systems / Signal Attributes

Converts one signal to the data type that another signal carries, and passes the result on – y = u, retyped to match ref. The reference exists to be asked about its type; its samples are never read, on either side of the bridge.

On this tree's signals the conversion changes no value, and the block says so rather than pretending otherwise. Every ICore wire carries a matrix of doubles, so the type on offer is always double, and a double converted to a double is itself. The output is therefore the signal input unchanged. This is exactly what Simulink's own block does when its reference is a double – which here it always is – so the block is a faithful restriction of it, not a simplification.

Ports

• ref – the type reference. This is the FIRST input, which is the reverse of the obvious reading and was measured against R2026a rather than assumed. Any size [m,n]; its values are discarded, so nothing it carries can reach the output.
• u – the signal to convert, the SECOND input. Any size [m,n].
• Output – y, the same size and the same values as u. Its size follows u alone; the reference's size is not consulted.

Parameters

• Rounding Method – how a value that does not land on the target type would be rounded: Ceiling, Convergent, Floor, Nearest, Round, Simplest or Zero. Defaults to Floor, as in Simulink. Inert here, measured: with a double reference there is no narrower type to round to, so every setting leaves the output identical. It is carried so that a model crossing the bridge keeps it.
• Saturate On Overflow – on clamps a value at the target type's limits, off lets it wrap. Defaults to off, as in Simulink. Inert here, for the same reason: a double has no limits to reach.
• Conversion Mode – Real World Value converts the value a signal stands for; Stored Integer reinterprets the raw stored number. Defaults to Real World Value. Inert here: with no scaling anywhere the two readings coincide.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. This one is ICore's own: the Simulink block defines no sample-time parameter, so a rate set here stays on the ICore side and is reported rather than written into an exported model.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every one of them emits a copy of the signal input and never touches the reference. None of the three parameters reaches the generated code: they select a conversion that does not happen, so emitting them would cost every target a branch that can never be taken. The three HDL targets are trivially synthesizable – there is no arithmetic to quantize.

Simulink bridge

Import and export, mapped to simulink/Signal Attributes/Data Type Conversion Inherited. "Rounding Method" maps to RndMeth (all seven values, one for one), "Saturate On Overflow" to DoSatur and "Conversion Mode" to ConvertRealWorld. All three are 1:1 and therefore lossless in both directions, so a model that arrives with a non-default setting leaves with it.

Note that this block's ConvertRealWorld values are Real World Value and Stored Integer, without the (RWV) and (SI) suffixes the plain Data Type Conversion block uses. That is measured, and it matters: setting a value a Simulink block does not accept is a hard error that aborts the generated script.

The Simulink block defines no SampleTime, so the bridge deliberately writes none – the same reason. A block configured with an explicit positive rate reports that the rate did not cross.

Notes

• Algebraic, with no state: the output is the signal input, sample for sample.
• The reference is consulted for its type and nothing else. A model that needs the reference's values wants a different block; nothing on this one can carry them.
• Deliberately carries no state space, even though the identity is linear. Absorbing this block into a neighbour would erase a declaration the user made about the wire, and would have to account for a second input that contributes nothing – so model reduction reports it as unmergeable, the same choice Signal Specification makes.
• To convert to a type named outright rather than one taken from a reference signal, use Data Type Conversion; that block does change values, rounding and clamping at the target type's limits.