Upfirdn — Control Systems/Resampling

Upfirdn

Control Systems / Resampling

A rational rate change by L/M in one stage: insert L−1 zeros between input samples, filter once, and keep one sample in every M, holding each kept sample until the next. One filter does both jobs – it removes the images the stuffing created AND the band the discarding would otherwise alias – which is why the three steps belong in one block rather than three.

v[k] = u[k] when k mod L = 0 and 0 otherwise; then w[k] = c₀·v[k] + c₁·v[k−1] + … + c_n·v[k−n]; then y[k] = w[k] when k mod M = 0 and y[k] = y[k−1] in between. The sample index k counts from 0 at the start of the run, so the first tick both takes a sample and publishes one, and the filter's delay line starts empty.

The block runs at the fast rate – L times the input's – and its kept samples come out at the input rate times L/M. Drive it from a source running at L times this block's "Sampling Time (s)".

Ports

• Input – the signal u to resample, of any size [m,n]. Every entry is stuffed, filtered and kept on the same ticks, each carrying its own delay line; the entries do not interact.
• Output – the resampled-and-held signal y, the SAME size [m,n] as the input, at the block's own (fast) rate.

Parameters

• FIR Coefficients – c₀…c_n, the single filter's impulse response as a non-empty vector, first entry multiplying the current stuffed sample and last the oldest. This block does not design the filter: pair it with FIR Window Design, or pass a response designed elsewhere. Defaults to [1 1 1], a boxcar of length L which at the default factors holds each input sample across its L stuffed slots – the crudest correct interpolation, and the easiest to read.
• Upsampling Factor – L, the number of ticks per input sample, a whole number of 1 or more. At L = 1 nothing is stuffed. Defaults to 3.
• Downsampling Factor – M, the number of ticks per kept sample, a whole number of 1 or more. At M = 1 every filtered sample is kept. Defaults to 2.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. On this block that is the fast rate: a new input sample is taken every Lth step of it and a sample is published every Mth.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The coefficients and both factors are baked into the core at export time rather than exposed as tunable parameters: the tap count also fixes how many state words the core carries, and a rate change whose ratio could be retuned on a built core would be a different block.

The three HDL targets are not simulation-only. The arithmetic is one multiply-accumulate over a short constant tap list, which the Q16.16 datapath carries without difficulty; what those columns do carry is the port's own quantization, which is a property of an HDL signal rather than of this block. The delay line is emitted unrolled, so a long filter on a large signal is a large entity: the state word count is n×m×p for a filter with n taps behind the current sample on an [m,p] signal, plus one word per signal entry for the retained sample.

Two things every target writes the same way. The stuffed zero is shifted into the delay line explicitly, because a wire holds its upstream value and a body that read the port every tick would filter a held staircase. And the kept sample publishes the freshly computed sum rather than reading back the register it is storing into, because an HDL register write is deferred to the clock edge.

Simulink bridge

Neither imported nor exported, and the reason is that its counterpart has no sample-based mode at all. dspmlti4/FIR Rate Conversion is a real DSP System Toolbox block that computes exactly this, and it is named here rather than declared absent – but its dialog carries no InputProcessing parameter: it is frame-based, and under rateMode = Enforce single-rate processing it requires an input frame whose row count is a multiple of M, refusing a one-element signal in as many words. An ICore wire carries one sample per tick, so there is no configuration of that block for a bridge to name.

Reproduce it instead by running the SOURCE at L times this block's "Sampling Time (s)" and reading the kept samples, which is what upfirdn returns.

Notes

• Stateful: the filter's delay line over the stuffed stream, the retained sample, and TWO phase counters – one mod L for which tick takes a sample, one mod M for which tick publishes. All start from zero at the beginning of every run, so a re-run reproduces the stream exactly.
• Discrete by nature – the phases advance once per sample, so the block always takes its period from its own "Sampling Time (s)" and is never pushed through a continuous solver's intermediate stages.
• No state space, deliberately. Both which sample enters the filter and which leaves it depend on WHEN it arrives, so the block is periodically time-varying and no single A/B/C/D describes it.
• Upfirdn vs. Interpolate vs. Decimate. All three are the same delay line with different things switched on: Interpolate stuffs and filters (M = 1), Decimate filters and keeps (L = 1), and this block does both with ONE filter between them – the only way to change the rate by a ratio that is not a whole number without filtering twice. At L = M it is a plain FIR filter with a longer name.
• The filter's gain is yours to choose. Stuffing divides the average power by L, so the response is usually given a passband gain of L to put it back – which is why the default [1 1 1] sums to 3 at the default L of 3 rather than to 1.