Unit System Configuration — Control Systems/Ports And Subsystems
Control_Systems/Ports_And_Subsystems/Unit_System_Configuration · 0 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Unit System Configuration
Control Systems / Ports And Subsystems
Narrows which unit systems the subsystem it is placed in may use for the units on its ports: SI, English, SI (extended) and CGS. A subsystem input or output whose unit none of the allowed systems holds is reported with a warning when the model is built – at the level the block is on, and in the subsystems below it. It is a check only: it never stops a run and never changes a value; a unit conversion still happens as it would without it.
Ports
- None.
Parameters
- Unit Systems – the allowed systems, separated by semicolons, any of
SI,English,SI (extended)andCGS. Default all four, as in Simulink. A name that is none of them is reported. - Allow All Unit Systems – On (the default) allows every unit, whatever Unit Systems says; Off applies the list.
- Sampling Time (s) – not used: the block computes nothing. It does not cross to Simulink, whose block has no rate parameter.
Which units each system holds
As R2026a's units database places ICore's units (measured): SI holds the kelvin and degree Celsius, the radian and rad/s, the metre and its multiples, m/s, km/s and m/s², the kilogram and gram, newton, pascal, joule, watt and N·m, and the second and millisecond. English holds the Fahrenheit and Rankine degrees, the radian, degree, revolution, rad/s, deg/s and rpm, the inch, foot, mile and nautical mile, ft/s, mph, knot, in/s, ft/min and ft/s², the pound-mass and slug, pound-force, psi, psf and atmosphere, the BTU, lbf·ft, and the second, millisecond, minute and hour. SI (extended) is SI with the degree, revolution, deg/s, rpm, km/h, knot, nautical mile, bar, the watt-hour and kilowatt-hour, the calorie, minute and hour. CGS holds the radian and rad/s, the metre and its multiples, m/s, km/s and m/s², the kilogram and gram, and the second and millisecond.
The warning
In Simulink's words: One or more of the units in the unit expression 'ft' at input port 1 of '…' is not in one of the allowed unit systems 'SI'. Two Unit System Configuration blocks in one subsystem are refused, as Simulink refuses the second one. A subsystem below that holds its own block is checked by that one instead.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, as a named body that does nothing: the check is made when the model is built, and Simulink's block is virtual.
Simulink bridge
Import and export, mapped to simulink/Ports & Subsystems/Unit System
Configuration: Unit Systems ↔ the cell UnitSystems
and Allow All Unit Systems ↔ AllowAllUnitSystems.
Notes
- Only subsystem input and output gates are checked, because they are where a unit is assigned. A gate with no unit is not checked. A gate whose unit is not in ICore's unit table is not checked either, since ICore's unit check already reports that unit.
- A warning is given once each time the model is built, even when several gates would repeat the same text.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Ports_And_Subsystems/Unit_System_Configuration |
| family | Control_Systems/Ports_And_Subsystems |
| solver environment class | ICoreBlock_0_Control_Systems_1_Ports_And_Subsystems_2_Unit_System_Configuration |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Ports_And_Subsystems/Unit_System_Configuration/ICoreBlock_0_Control_Systems_1_Ports_And_Subsystems_2_Unit_System_Configuration.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Ports_And_Subsystems/Unit_System_Configuration/ICoreBlock_0_Control_Systems_1_Ports_And_Subsystems_2_Unit_System_Configuration.h |
| default size on canvas | 80 × 60 px |
| ports at insert | 0 in, 0 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
The constructor creates no port explicitly — the port list comes from registerInitialPorts (0 in, 0 out) or from the block's configuration.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Unit Systems | SI; English; SI (extended); CGS | UnitSystems |
Allow All Unit Systems | On%~%Off~~On | AllowAllUnitSystems |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Ports & Subsystems/Unit System Configuration |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Unit Systems | UnitSystems | passes through |
Allow All Unit Systems | AllowAllUnitSystems | On → on, Off → off |
Caveat (shown to the user): UnitSystems is a cell of system names on the Simulink side and a semicolon list here; the block is virtual and has NO SampleTime parameter
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Unit System Configuration -- which unit systems a subsystem's ports may use Measured on R2026a (FEATURES_TO_ADD.md §F.BF20, and for this row on 2026-10-02):
BlockType=UnitConfiguration, no ports, virtual, two parameters:UnitSystems, a CELL of system names (default {'SI','English','SI (extended)','CGS'}), andAllowAllUnitSystems(default on); no SampleTime. With AllowAll off, a port unit inside its subsystem -- at its level and in a subsystem nested below -- that none of the systems holds draws the warning "One or more of the units in the unit expression 'ft' at input port 1 of '.../O' is not in one of the allowed unit systems 'SI'" (Simulink:Unit:DisallowedUnitSystemUsage); a unit in the PARENT level is not checked; it converts and runs all the same (BF20.1). AllowAll on checks nothing. A system name the database does not know warns "Unit systems 'Bogus' specified by Unit Configuration block ... are not in the units database". A second one in a subsystem is refused (Simulink:StateConfigurator:DuplicateConfiguratorBlocks).Which units each system holds was measured unit by unit over ICore's unit table (one model, the unit on an Outport inside a configured subsystem, each of the four systems alone): the table below is that measurement.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.