Generated reference › FIR Window Design — Control Systems/Polynomials
kind: generated#block#control-systems-polynomials

FIR Window Design — Control Systems/Polynomials

FIR

Control_Systems/Polynomials/FIR_Window_Design · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

FIR Window Design

Control Systems / Polynomials

Designs a finite impulse response filter of order N by the window method and reports its N + 1 taps, with the cutoff arriving on a port. It is MATLAB's fir1: the ideal brick-wall impulse response, truncated to N + 1 samples, multiplied by a window and scaled so the gain is 1 in the passband.

With Wn = 2fc/fs and tk = k − N/2 the tap's distance from the centre, every tap is one sine of the cutoff: bk = wk·sin(πWntk) / (πtk).

It designs; it does not filter. Unlike the five IIR designers in this family it has one output, because an FIR filter's denominator is the scalar 1: feed b to Discrete / Transfer Fcn Direct Form II Time Varying's Num port and a Constant of 1 to its Den. The two need not be the same length.

Ports

  • fc – the cutoff frequency in Hz. Scalar. Clamped into (0, fs/2) – see Notes.
  • b – the filter's taps, in the order a delay line consumes them, as a column of N + 1 entries. The response is symmetric, so the vector reads the same forwards and backwards.

Parameters

  • Order – N, a whole number from 1 to 64. The output is N + 1 long and the group delay is N/2 samples. Default 12.
  • Filter Type – which ideal response is truncated:
    • Lowpass – passes below the cutoff, scaled to unity at zero frequency. Default.
    • Highpass – passes above it, scaled to unity at Nyquist. Requires an even order – see Notes.
  • Window – which taper multiplies the truncated response. All four are the symmetric forms, as MATLAB's are:
    • Hamming – 0.54 − 0.46·cos(2πk/N). Default, and fir1's.
    • Hann – 0.5 − 0.5·cos(2πk/N); the end taps are zero.
    • Blackman – 0.42 − 0.5·cos(2πk/N) + 0.08·cos(4πk/N); the lowest sidelobes and the widest transition.
    • Rectangular – no taper at all, which is the plain truncated sinc and the worst sidelobes.
  • Sample Rate (Hz) – fs, the rate the filter is designed FOR, and the rate the cutoff is measured against. Strictly positive. This is not the block's own rate. Default 100.
  • Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The order, the type, the window and the rate are structural and are baked into the generated body, so nothing is exposed as a tunable parameter on the generated core; every tap's window value and its two constants are inlined. No generated body contains a branch: whether a tap sits at the centre is decided by the order, so the centre tap is emitted as its own expression rather than tested for.

The three HDL targets are simulation-only, and deliberately: a sine and a reciprocal do not belong in a Q16.16 datapath. Both are evaluated in real and the values convert at the port boundary, which is what the Trigonometry family does for the same reason. The seven software targets are exact.

Simulink bridge

None (Support::None). fir1 is a MATLAB function, and the Simulink blocks that carry a windowed-sinc design – Lowpass FIR Filter Design and its Highpass, Bandpass and Bandstop siblings, in the DSP System Toolbox – do the design internally and expose no part of it: each takes a signal in and gives a filtered signal out, so none has taps a diagram could read. There is therefore no library path this block could name. The bridge reports it rather than dropping it silently, and it has no parity testbench; code export verification still covers it across all ten languages. No configuration of it crosses either, including "Sampling Time (s)", which has no counterpart to be written to.

Notes

  • Algebraic, with no state: the output depends only on the current input.
  • An odd order is refused for a highpass, and MATLAB does something else. A symmetric FIR of odd order has a zero at Nyquist and so cannot pass the top of the band. fir1 quietly increments the order and warns; this block refuses, because its output size is Order + 1 and a silently longer vector is worse than a stated refusal. Measured: fir1(9, Wn, 'high') returns eleven taps, not ten.
  • Nothing divides by the cutoff. Writing Wn·sinc(Wnt) as sin(πWnt)/(πt) cancels Wn out of the divisor, so a cutoff of zero is an ordinary value and not a special case.
  • The two scalings are different rules, not one. A lowpass is divided by Σb and a highpass by |Σ(−1)kbk| – unity at zero frequency and unity at Nyquist respectively, which is what fir1 does.
  • The clamp is a live branch, not a safety net. fc is clamped into (0, fs/2) by (|x−lo| − |x−hi| + lo + hi)/2, branchless and identical in this block and in all ten emitted bodies, so they agree bit for bit.
  • The windows are the SYMMETRIC forms, as MATLAB's hamming, hann and blackman are by default. The periodic forms differ in the divisor (N rather than N − 1 points) and would put the design a visible distance from fir1.
  • Measured against R2026a, at fs = 4 Hz over orders 8, 9, 16, 21 and 32, cutoffs 0.7 Hz and 1.1 Hz, all four windows and both types: the largest disagreement with fir1 on any tap is 3.3e−16 – measured through a harness carrying the shipped C++, not the prototype it was written from.
  • No state space: one scalar in and one vector out, so there is no A/B/C/D to merge and model reduction correctly declines it.

Code facts#

FactValue
registered typeControl_Systems/Polynomials/FIR_Window_Design
familyControl_Systems/Polynomials
solver environment classICoreBlock_0_Control_Systems_1_Polynomials_2_FIR_Window_Design
sourcesrc/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Polynomials/FIR_Window_Design/ICoreBlock_0_Control_Systems_1_Polynomials_2_FIR_Window_Design.cpp
headersrc/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Polynomials/FIR_Window_Design/ICoreBlock_0_Control_Systems_1_Polynomials_2_FIR_Window_Design.h
default size on canvas140 × 72 px
ports at insert1 in, 1 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDoublefc
2outICoreDoubleb

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Order12—
Filter TypeLowpass%~%Highpass~~Lowpass—
WindowHamming%~%Hann%~%Blackman%~%Rectangular~~Hamming—
Sample Rate (Hz)100—

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::None
Simulink path—
port-count rulePortsParam::None
SampleTime parameteryes

Caveat (shown to the user): designing a windowed-sinc FIR filter is a MATLAB function (fir1), not a Simulink library block -- the blocks that carry the design, Lowpass FIR Filter Design and its Highpass, Bandpass and Bandstop siblings in the DSP System Toolbox, take a signal in and give a filtered signal out, so none exposes the taps this block emits and there is no path a diagram could name; the block is reported rather than dropped when a model crosses

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

FIR Window Design -- fir1 on a wire, with the cutoff on a port The classical windowed sinc, and the only designer in this family with no denominator.

With Wn = 2*fc/fs and t_k = k - N/2, every tap is ONE sine of the cutoff:

tap_k = C_k * sin(P_k * fc) C_k = window_k / (pi * t_k), P_k = 2*pi*t_k/fs tap_M = window_M * (2/fs) * fc the centre tap, when the order is even

because Wn * sinc(Wn*t) = sin(pi*Wn*t)/(pi*t) -- writing it that way cancels Wn out of the divisor, so nothing divides by the cutoff and a cutoff of zero is an ordinary value rather than a special case. A highpass negates every C_k and puts 1 - Wn at the centre, the sinc of an integer t being zero everywhere else.

The scaling is MATLAB's, and it is two different rules: SUM(b) for a lowpass (unity at zero frequency) and |SUM (-1)^k b_k| for a highpass (unity at Nyquist). The alternating sign is folded into the constants at export time, so a generated body sums once either way.

Verified against MATLAB R2026a rather than asserted, at fs = 4 Hz over orders 8, 9, 16, 21 and 32, cutoffs 0.7 Hz and 1.1 Hz, all four windows and both types: the largest disagreement with fir1 on any tap is 3.3e-16, measured through a standalone harness carrying the SHIPPED C++ rather than the Python prototype it was written from -- which read 5.6e-16, so the two differ and the one quoted is the one that ships. The window shapes were pinned separately against hamming(8), hann(8) and blackman(8), all three at 2.8e-16 or better.

Sample results#

FIR Window Design — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sampleFIR Window Design — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample0.010.01050.0110.01150.012-2-10123inputoutput
tin ICoreDouble-Out-0out ICoreDouble-Out-0 [13x1] entry 0
0-2[0.0122, 0.02159, 0.04726, 0.08232]…
0.40.5[0.01214, 0.02152, 0.04718, 0.08228]…
0.8-2[0.0122, 0.02159, 0.04726, 0.08232]…
1.20.5[0.01214, 0.02152, 0.04718, 0.08228]…
1.6-2[0.0122, 0.02159, 0.04726, 0.08232]…
20.5[0.01214, 0.02152, 0.04718, 0.08228]…
2.4-2[0.0122, 0.02159, 0.04726, 0.08232]…
2.80.5[0.01214, 0.02152, 0.04718, 0.08228]…
3.2-2[0.0122, 0.02159, 0.04726, 0.08232]…
3.60.5[0.01214, 0.02152, 0.04718, 0.08228]…
4-2[0.0122, 0.02159, 0.04726, 0.08232]…
4.40.5[0.01214, 0.02152, 0.04718, 0.08228]…
4.8-2[0.0122, 0.02159, 0.04726, 0.08232]…
5.20.5[0.01214, 0.02152, 0.04718, 0.08228]…

Every 4th of 60 samples, from the table stimulus.

The same rig also ran:

StimulusWhat it isOutput range
impulseImpulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair)0.01196 … 0.0122
rampRamp: slope 1 from t = 00.005192 … 0.0122
sineSine Wave: amplitude 1, 2 rad/s, no phase, no bias0.01196 … 0.0122
stepStep: 0 -> 1 at t = 1 s0.01196 … 0.0122

Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample

Category static · sample time 0.1 · 60 steps · commit a296f900c621d6e0771bec30f4bf0f90916d8474 · produced by docsSample --out <folder> --blocks FIR_Window_Design --steps 60 · data docs/generated/samples/Control_Systems__Polynomials__FIR_Window_Design.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).