Generated reference › FIR Least Squares Design — Control Systems/Polynomials
kind: generated#block#control-systems-polynomials

FIR Least Squares Design — Control Systems/Polynomials

LS

Control_Systems/Polynomials/FIR_Least_Squares_Design · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

FIR Least-Squares Design

Control Systems / Polynomials

Designs a linear-phase finite impulse response filter of order N by weighted least squares and reports its N + 1 taps, with the centre of the transition band arriving on a port. It is MATLAB's firls for two bands: the taps minimise Wp·∫pass|H − 1|² + Ws·∫stop|H|², the transition between the bands being a region the error ignores.

With fc on the port and tw the transition width, the bands are [0, fc − tw/2] and [fc + tw/2, fs/2], which is firls(N, [0 fc−tw/2 fc+tw/2 fs/2]/(fs/2), [1 1 0 0], [Wp Ws]) for a lowpass and the same with [0 0 1 1] and the weights swapped for a highpass. The minimiser is one linear solve whose matrix moves with the band edges, so the design is redone on every step.

It designs; it does not filter. Feed b to Discrete / Transfer Fcn Direct Form II Time Varying's Num port and a Constant of 1 to its Den, as for FIR Window Design.

Ports

  • fc – the centre of the transition band, in Hz. Scalar. Clamped into [tw, fs/2 − tw] – see Notes.
  • b – the filter's taps, in the order a delay line consumes them, as a column of N + 1 entries. The response is symmetric, so the vector reads the same forwards and backwards.

Parameters

  • Order – N, a whole number from 1 to 64. The output is N + 1 long and the group delay is N/2 samples. An even order is a type I filter and an odd one a type II, whose response is zero at Nyquist. Default 12.
  • Filter Type – which band is the passband:
    • Lowpass – desired response 1 below the transition and 0 above it. Default.
    • Highpass – 0 below and 1 above. Requires an even order – see Notes.
  • Transition Width (Hz) – tw, the width of the don't-care region centred on fc. Strictly positive and below fs/4, and Order × tw must not exceed 6 fs – see Notes. Default 10.
  • Passband Weight – Wp, how much an error in the passband costs. Strictly positive. Default 1.
  • Stopband Weight – Ws, the same for the stopband; raising it trades passband ripple for attenuation. Strictly positive. Default 1.
  • Sample Rate (Hz) – fs, the rate the filter is designed FOR and the rate the band edges are measured against. Strictly positive. This is not the block's own rate. Default 100.
  • Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every setting is structural and is baked into the generated body, so nothing is exposed as a tunable parameter on the generated core. The body is the whole design – the band integrals, the Cholesky factorisation of the least-squares system and the two triangular solves – as loops over local arrays, and it is the same program the block runs, printed once per language rather than transcribed ten times.

The three HDL targets are simulation-only, and deliberately: a sine, a square root and a linear solve do not belong in a Q16.16 datapath. The design runs in real (VHDL inside a procedure) and the taps convert at the port boundary. The seven software targets are exact.

Simulink bridge

None (Support::None). firls is a MATLAB function and no Simulink library block carries it. Every design block in the DSP System Toolbox's filter-design library is a filter – signal in, filtered signal out – so none exposes taps a diagram could read: the Lowpass/Highpass FIR Filter Design blocks are window-method, the Lowpass Filter and Highpass Filter blocks design from ripple and attenuation targets, and Digital Filter Design is an interactive designer with no parameter a model could set. There is therefore no library path this block could name. The bridge reports it rather than dropping it silently, and it has no parity testbench; code export verification still covers it across all ten languages. No configuration of it crosses either, including "Sampling Time (s)", which has no counterpart to be written to.

Notes

  • Algebraic, with no state: the output depends only on the current input.
  • The port carries the CENTRE of the transition, not a band edge, so a lowpass and a highpass on the same wire split the spectrum in the same place. It is clamped into [tw, fs/2 − tw] by (|x−lo| − |x−hi| + lo + hi)/2, branchless and identical in the block and in all ten emitted bodies, so each band always keeps at least half a transition width.
  • An odd order is refused for a highpass, and MATLAB does something else. A symmetric FIR of odd order has a zero at Nyquist and so cannot pass the top of the band; firls quietly increments the order and warns, and this block refuses, because its output size is Order + 1. Measured: firls(9, ...) with a highpass response returns eleven taps, not ten.
  • The order-times-width limit is measured, and it is where MATLAB stops being an answer. A transition wide for its order makes a design whose error is at the floor of double precision, and there the least-squares matrix is numerically singular: its condition number grows like e0.6·N·D (D the width as a fraction of Nyquist) and MATLAB's own solve warns that the matrix is singular. Inside the limit the block agrees with firls to 9.9e−9 or better on every tap; past it the two can differ by whole units.
  • Measured against R2026a, 1362 designs across the domain: worst disagreement with firls on any tap 9.9e−9, reached at the domain boundary where the system's condition number is largest – and numpy's LAPACK solve of the same matrix lands as far from MATLAB, so the spread is the problem's and not the block's. Away from the boundary, at order 16 or less, it is 5e−15.
  • No state space: one scalar in and one vector out, so there is no A/B/C/D to merge and model reduction correctly declines it.

Code facts#

FactValue
registered typeControl_Systems/Polynomials/FIR_Least_Squares_Design
familyControl_Systems/Polynomials
solver environment classICoreBlock_0_Control_Systems_1_Polynomials_2_FIR_Least_Squares_Design
sourcesrc/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Polynomials/FIR_Least_Squares_Design/ICoreBlock_0_Control_Systems_1_Polynomials_2_FIR_Least_Squares_Design.cpp
headersrc/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Polynomials/FIR_Least_Squares_Design/ICoreBlock_0_Control_Systems_1_Polynomials_2_FIR_Least_Squares_Design.h
default size on canvas140 × 72 px
ports at insert1 in, 1 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDoublefc
2outICoreDoubleb

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Order12—
Filter TypeLowpass%~%Highpass~~Lowpass—
Transition Width (Hz)10—
Passband Weight1—
Stopband Weight1—
Sample Rate (Hz)100—

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::None
Simulink path—
port-count rulePortsParam::None
SampleTime parameteryes

Caveat (shown to the user): designing a least-squares FIR filter is a MATLAB function (firls), not a Simulink library block -- every design block in the DSP System Toolbox's filter-design library is a filter (signal in, filtered signal out) that exposes no taps, and its Digital Filter Design block is an interactive designer with no settable parameter, so there is no path a diagram could name; the block is reported rather than dropped when a model crosses

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

FIR Least-Squares Design -- firls on a wire, with the transition centre on a port The taps that minimise the weighted integral of the squared error between the response and an ideal lowpass or highpass, over two bands with a don't-care transition between them:

band edges [0, fc - tw/2] and [fc + tw/2, fs/2] fc on the port, tw a setting error Wp * INT(passband) |H - 1|^2 + Ws * INT(stopband) |H|^2

which is firls(N, [0 fc-tw/2 fc+tw/2 fs/2]/(fs/2), [1 1 0 0], [Wp Ws]) and its highpass mirror. The minimiser is one linear solve, G a = b, whose matrix holds sine integrals at the band edges -- so it moves with the port, and the solve runs on every step, here and in all ten generated languages, from the program in Polynomials/ICoreFirOptimalDesignSupport.

Verified against MATLAB R2026a rather than asserted: the shipped program, run through a standalone harness, against firls over 1362 designs inside the block's domain (orders 3 to 64, both types, three weight pairs, transition centres across the clamp range and widths up to the domain limit). Worst disagreement on any tap 9.9e-9, at the domain boundary where cond(G) is largest -- and numpy's LAPACK solve of the same matrix lands as far from MATLAB, so that is the problem's conditioning and not the transcription. Away from the boundary, at order 16 or less, it is 5e-15.

Sample results#

FIR Least Squares Design — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sampleFIR Least Squares Design — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample-0.0095-0.009-0.0085-2-10123inputoutput
tin ICoreDouble-Out-0out ICoreDouble-Out-0 [13x1] entry 0
0-2[-0.009076, 0.003878, 0.0356, 0.0837]…
0.40.5[-0.009076, 0.003878, 0.0356, 0.0837]…
0.8-2[-0.009076, 0.003878, 0.0356, 0.0837]…
1.20.5[-0.009076, 0.003878, 0.0356, 0.0837]…
1.6-2[-0.009076, 0.003878, 0.0356, 0.0837]…
20.5[-0.009076, 0.003878, 0.0356, 0.0837]…
2.4-2[-0.009076, 0.003878, 0.0356, 0.0837]…
2.80.5[-0.009076, 0.003878, 0.0356, 0.0837]…
3.2-2[-0.009076, 0.003878, 0.0356, 0.0837]…
3.60.5[-0.009076, 0.003878, 0.0356, 0.0837]…
4-2[-0.009076, 0.003878, 0.0356, 0.0837]…
4.40.5[-0.009076, 0.003878, 0.0356, 0.0837]…
4.8-2[-0.009076, 0.003878, 0.0356, 0.0837]…
5.20.5[-0.009076, 0.003878, 0.0356, 0.0837]…

Every 4th of 60 samples, from the table stimulus.

The same rig also ran:

StimulusWhat it isOutput range
impulseImpulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair)-0.009076 … -0.009076
rampRamp: slope 1 from t = 0-0.009076 … -0.009076
sineSine Wave: amplitude 1, 2 rad/s, no phase, no bias-0.009076 … -0.009076
stepStep: 0 -> 1 at t = 1 s-0.009076 … -0.009076

Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample

Category static · sample time 0.1 · 60 steps · commit 383c0ecf1501cf1d43d89b8f688fc2fcad5e9b52 · produced by docsSample --out <folder> --blocks Ideal_Airspeed_Correction WGS84_Gravity_Model Linear_Regression_Predictor Linear_Classifier_Predictor Crossover_Pilot_Model Precision_Pilot_Model Tustin_Pilot_Model FIR_Least_Squares_Design FIR_Equiripple_Design Cartesian_To_Keplerian_Elements Keplerian_Elements_To_Cartesian --steps 60 · data docs/generated/samples/Control_Systems__Polynomials__FIR_Least_Squares_Design.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).