Elliptic Design — Control Systems/Polynomials

Elliptic Design

Control Systems / Polynomials

Designs a digital elliptic (Cauer) filter of order N and reports its coefficients, with the cutoff arriving on a port. It is MATLAB's ellip: the analog prototype that ripples in both bands, denormalized to the cutoff and mapped to z by the bilinear transform prewarped at that same cutoff, so the passband edge sits at exactly f_c.

An elliptic filter buys the steepest transition of any prototype in this family at a given order, and pays for it with ripple everywhere and the worst group delay of the four. It is what to reach for when the order is the thing being minimized. Everything follows from one number, T = tan(πf_c/f_s); both polynomials are then divided by a[0], so the denominator is monic and the answer is MATLAB's exactly.

It designs; it does not filter. Feed b and a to Discrete / Transfer Fcn Direct Form II Time Varying, which takes them on ports and so retunes with them.

Ports

• fc – the passband-edge frequency in Hz, the point at which the response has fallen by the full passband ripple. Scalar. Clamped into (0, f_s/2) – see Notes, the clamp is a live branch.
• b – the numerator's coefficients, descending powers of z, as a column of N + 1 entries.
• a – the denominator's, the same length, with a[0] = 1.

Parameters

• Order – N, a whole number from 1 to 8. Both outputs are N + 1 long. Default 3.
• Filter Type – which prototype mapping is used:
  • Lowpass – passes below the cutoff. Default.
  • Highpass – passes above it. The same prototype with s and 1/s exchanged, which swaps the roles of (z−1) and (z+1).
• Passband Ripple (dB) – R_p, the peak-to-peak depth of the passband ripple in decibels. Strictly positive, from 1e−4 to 60. Default 1.
• Stopband Attenuation (dB) – R_s, how far down the stopband ripple is held, in decibels. From 3 to 200, and it must be strictly greater than the passband ripple – there is no prototype otherwise, and ellipap refuses the same pair. Default 40.
• Sample Rate (Hz) – f_s, the rate the filter is designed FOR, and the rate the cutoff is measured against. Strictly positive. This is not the block's own rate. Default 100.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The order, the type, both ripple figures and the rate are structural and are baked into the generated body, so nothing is exposed as a tunable parameter on the generated core; the prototype coefficients and the integer expansions are inlined. No generated core contains a complex number: the elliptic prototype is built in complex arithmetic at configuration time and what is emitted is the real polynomial it produces.

The three HDL targets are simulation-only, and deliberately: a tangent and a reciprocal do not belong in a Q16.16 datapath. Both are evaluated in real and the values convert at the port boundary, which is what the Trigonometry family does for the same reason. The seven software targets are exact.

Simulink bridge

None (Support::None). ellip is a MATLAB function, and the two Simulink blocks that carry an elliptic design – Analog Filter Design and Lowpass IIR Filter Design, both in the DSP System Toolbox's design library – do the design internally and expose no part of it: each takes a signal in and gives a filtered signal out, so neither has coefficients a diagram could read. There is therefore no library path this block could name. The bridge reports it rather than dropping it silently, and it has no parity testbench; code export verification still covers it across all ten languages. No configuration of it crosses either, including "Sampling Time (s)", which has no counterpart to be written to.

Notes

• Algebraic, with no state: the output depends only on the current input.
• The cutoff is the PASSBAND edge, as on Butterworth Design and Chebyshev Type I Design – and not as on Chebyshev Type II Design, whose port carries a stopband edge. The two ripple figures are independent of it.
• b is not a scaled corner expansion. Like Chebyshev Type II, this prototype has finite zeros on the imaginary axis; they map onto the unit circle, so the digital numerator is palindromic and carries true nulls in the stopband.
• The even-order response does not start at 1. As with Chebyshev Type I, an odd order is 1 at zero frequency and an even order starts a whole ripple low, at 10^−R_p/20. That is ellip's convention and it is carried here rather than normalized away.
• The clamp is a live branch, not a safety net. f_c is clamped into (0, f_s/2) by (|x−lo| − |x−hi| + lo + hi)/2, branchless and identical in this block and in all ten emitted bodies, so they agree bit for bit. It exists because VHDL's TAN raises an error at π/2, which stops a simulation rather than returning a bad number. A cutoff at or below zero therefore designs at the bottom of the band rather than failing: T → 0, the numerator collapses to its own floor and the denominator becomes (z−1)^N.
• Measured against R2026a, at f_s = 4 Hz over orders 1 to 8, cutoffs 0.7 Hz and 1.1 Hz and both types: the largest disagreement with ellip on any coefficient is 8.9e−15 at order 6, and 5.6e−16 at order 3 – the closest of the four prototypes here to its reference at high order, which is worth saying because it is the one built in complex arithmetic.
• No state space: one scalar in and two vectors out, so there is no A/B/C/D to merge and model reduction correctly declines it.