Chebyshev Type II Design — Control Systems/Polynomials

Chebyshev Type II Design

Control Systems / Polynomials

Designs a digital Chebyshev Type II filter of order N and reports its coefficients, with the cutoff arriving on a port. It is MATLAB's cheby2: the analog flat-passband, equiripple-stopband prototype, denormalized to the cutoff and mapped to z by the bilinear transform prewarped at that same cutoff, so the stopband edge sits at exactly f_c.

A Type II filter is the Type I turned inside out: the passband is flat and the ripple lives in the stopband, bounded by the attenuation asked for. Everything follows from one number, T = tan(πf_c/f_s); both polynomials are then divided by a[0], so the denominator is monic and the answer is MATLAB's exactly.

It designs; it does not filter. Feed b and a to Discrete / Transfer Fcn Direct Form II Time Varying, which takes them on ports and so retunes with them.

Ports

• fc – the stopband-edge frequency in Hz: the point at which the response first reaches the stated attenuation. Scalar. This is not a passband edge – see Notes. Clamped into (0, f_s/2).
• b – the numerator's coefficients, descending powers of z, as a column of N + 1 entries.
• a – the denominator's, the same length, with a[0] = 1.

Parameters

• Order – N, a whole number from 1 to 8. Both outputs are N + 1 long. Default 3.
• Filter Type – which prototype mapping is used:
  • Lowpass – passes below the cutoff. Default.
  • Highpass – passes above it. The same prototype with s and 1/s exchanged, which swaps the roles of (z−1) and (z+1).
• Stopband Attenuation (dB) – R_s, how far down the stopband ripple is held, in decibels. From 3 to 200. A larger value pushes the stopband further down and softens the transition. Default 40.
• Sample Rate (Hz) – f_s, the rate the filter is designed FOR, and the rate the cutoff is measured against. Strictly positive. This is not the block's own rate. Default 100.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The order, the type, the attenuation and the rate are structural and are baked into the generated body, so nothing is exposed as a tunable parameter on the generated core; the prototype coefficients and the integer expansions are inlined. This block inlines two weight matrices where the others in its family inline one and a vector, because its numerator is a polynomial.

The three HDL targets are simulation-only, and deliberately: a tangent and a reciprocal do not belong in a Q16.16 datapath. Both are evaluated in real and the values convert at the port boundary, which is what the Trigonometry family does for the same reason. The seven software targets are exact.

Simulink bridge

None (Support::None). cheby2 is a MATLAB function, and the two Simulink blocks that carry a Chebyshev Type II design – Analog Filter Design and Lowpass IIR Filter Design, both in the DSP System Toolbox's design library – do the design internally and expose no part of it: each takes a signal in and gives a filtered signal out, so neither has coefficients a diagram could read. There is therefore no library path this block could name. The bridge reports it rather than dropping it silently, and it has no parity testbench; code export verification still covers it across all ten languages. No configuration of it crosses either, including "Sampling Time (s)", which has no counterpart to be written to.

Notes

• Algebraic, with no state: the output depends only on the current input.
• The cutoff is the STOPBAND edge. On Butterworth Design and Chebyshev Type I Design the port carries a passband edge; here it carries the frequency at which the response first reaches R_s. Feeding a Type II block the frequency you would have given a Type I puts the transition in the wrong place and nothing else goes wrong, which is why it is stated here rather than left to the name.
• b is not a scaled corner expansion. This is the one prototype in the family with finite zeros – they sit on the imaginary axis at ±i/cosθ_k and map onto the unit circle, so the digital numerator is palindromic and carries true nulls in the stopband. On the sibling blocks it is a constant times (z+1)^N or (z−1)^N.
• The clamp is a live branch, not a safety net. f_c is clamped into (0, f_s/2) by (|x−lo| − |x−hi| + lo + hi)/2, branchless and identical in this block and in all ten emitted bodies, so they agree bit for bit. It exists because VHDL's TAN raises an error at π/2, which stops a simulation rather than returning a bad number. A cutoff at or below zero therefore designs at the bottom of the band rather than failing: T → 0, the numerator collapses and the denominator becomes (z−1)^N. The committed documentation sample shows it at f_c = 0 – b down at ±9.4e−10, its own floor rather than zero because this numerator is a polynomial whose constant term survives, against a = [1, −3, 3, −1] to eight digits.
• An odd order has one fewer zero than pole. The angle at θ = π/2 has no finite zero, so the numerator's degree is N − 1 there and its leading entry after mapping is not the one a count of poles would predict.
• Measured against R2026a, at f_s = 4 Hz over orders 1 to 8, cutoffs 0.7 Hz and 1.1 Hz and both types: the largest disagreement with cheby2 on any coefficient is 1.2e−14 at order 8, and 6.7e−16 at order 3.
• No state space: one scalar in and two vectors out, so there is no A/B/C/D to merge and model reduction correctly declines it.