Butterworth Design — Control Systems/Polynomials

Butterworth Design

Control Systems / Polynomials

Designs a digital Butterworth filter of order N and reports its coefficients, with the cutoff arriving on a port. It is MATLAB's butter: the analog maximally-flat prototype, denormalized to the cutoff and mapped to z by the bilinear transform prewarped at that same cutoff, so the digital response is 3 dB down at exactly f_c.

Everything follows from one number, T = tan(πf_c/f_s); both polynomials are then divided by a[0], so the denominator is monic and the answer is MATLAB's exactly.

It designs; it does not filter. Feed b and a to Discrete / Transfer Fcn Direct Form II Time Varying, which takes them on ports and so retunes with them. If you only want the filtered signal and never the coefficients, Continuous / Varying Lowpass Filter is the same Butterworth with the cutoff on a port and no coefficients to look at.

Ports

• fc – the cutoff frequency in Hz. Scalar. Clamped into (0, f_s/2) – see Notes, the clamp is a live branch.
• b – the numerator's coefficients, descending powers of z, as a column of N + 1 entries.
• a – the denominator's, the same length, with a[0] = 1.

Parameters

• Order – N, a whole number from 1 to 8. Both outputs are N + 1 long. Default 2.
• Filter Type – which prototype mapping is used:
  • Lowpass – passes below the cutoff. Default.
  • Highpass – passes above it. The same prototype with s and 1/s exchanged, which swaps the roles of (z−1) and (z+1) and makes the numerator (z−1)^N.
• Sample Rate (Hz) – f_s, the rate the filter is designed FOR, and the rate the cutoff is measured against. Strictly positive. This is not the block's own rate. Default 100.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The order, the type and the rate are structural and are baked into the generated body, so nothing is exposed as a tunable parameter on the generated core; the prototype coefficients and the integer expansions are inlined.

The three HDL targets are simulation-only, and deliberately: a tangent and a reciprocal do not belong in a Q16.16 datapath. Both are evaluated in real and the values convert at the port boundary, which is what the Trigonometry family does for the same reason. The seven software targets are exact.

Simulink bridge

None (Support::None). butter is a MATLAB function and the Signal Processing Toolbox it comes from ships no Simulink library at all. A sweep of the DSP System Toolbox design library on 2026-09-10 found only Analog Filter Design, which does the mapping internally and exposes no part of it – so there is no library path a diagram could name. The bridge reports this block rather than dropping it silently, and it therefore has no parity testbench; code export verification still covers it across all ten languages. No configuration of it crosses either, including "Sampling Time (s)", which has no counterpart to be written to.

Notes

• Algebraic, with no state: the output depends only on the current input.
• The cutoff is a PORT and MATLAB's is an argument. A cutoff taken from configuration would make this block a constant – nothing downstream could retune it. On a port it is a live design, which is what pairs it with Transfer Fcn Direct Form II Time Varying.
• The clamp is a live branch, not a safety net. f_c is clamped into (0, f_s/2) by (|x−lo| − |x−hi| + lo + hi)/2, branchless and identical in this block and in all ten emitted bodies, so they agree bit for bit. It exists because VHDL's TAN raises an error at π/2, which aborts a simulation rather than returning a bad number. A cutoff at or below zero therefore designs at the bottom of the band rather than failing: T → 0, the numerator vanishes and the denominator becomes (z−1)^N.
• Dividing by a[0] is safe here, and it is not on Bilinear Transform. a[0] is a sum of d_j·T^… terms with every d_j and T strictly positive, so it is at least 1 and cannot vanish. Polynomials / Bilinear Transform takes its analog denominator from a port, where the same quantity can pass through zero, so that block leaves the scale alone. The two blocks normalize differently on purpose.
• Measured against R2026a, at f_s = 4 Hz over orders 2 and 3 and cutoffs 0.7 and 1.1 Hz, both types: the largest disagreement with butter on any coefficient over those eight combinations is 2.2e−16.
• No state space: one scalar in and two vectors out, so there is no A/B/C/D to merge and model reduction correctly declines it.