Bessel Design — Control Systems/Polynomials

Bessel Design

Control Systems / Polynomials

Designs a digital Bessel filter of order N and reports its coefficients, with the cutoff arriving on a port. The prototype is MATLAB's besself – the reverse Bessel polynomial in its default phase normalization – denormalized to the cutoff and mapped to z by the bilinear transform prewarped at that same cutoff.

A Bessel filter buys the flattest group delay rather than the flattest magnitude: it passes a pulse with the least overshoot and ringing of any prototype in this family, and pays for it with a far gentler rolloff. Reach for it when the shape of a waveform matters more than how much of the band is rejected.

Everything follows from one number, T = tan(πf_c/f_s); both polynomials are then divided by a[0], so the denominator is monic.

It designs; it does not filter. Feed b and a to Discrete / Transfer Fcn Direct Form II Time Varying, which takes them on ports and so retunes with them.

Ports

• fc – the cutoff frequency in Hz: the frequency the delay is normalized against, so that the group delay near zero frequency is 1/(2πf_c) seconds. Scalar. Clamped into (0, f_s/2) – see Notes, the clamp is a live branch.
• b – the numerator's coefficients, descending powers of z, as a column of N + 1 entries.
• a – the denominator's, the same length, with a[0] = 1.

Parameters

• Order – N, a whole number from 1 to 8. Both outputs are N + 1 long. A higher order flattens the delay over a wider band; unlike the other prototypes here it does not buy much extra rolloff. Default 3.
• Filter Type – which prototype mapping is used:
  • Lowpass – passes below the cutoff. Default.
  • Highpass – passes above it. The same prototype with s and 1/s exchanged. Note that the flat-delay property is a lowpass property and does not survive the exchange – see Notes.
• Sample Rate (Hz) – f_s, the rate the filter is designed FOR, and the rate the cutoff is measured against. Strictly positive. This is not the block's own rate. Default 100.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The order, the type and the rate are structural and are baked into the generated body, so nothing is exposed as a tunable parameter on the generated core; the prototype coefficients and the integer expansions are inlined.

The three HDL targets are simulation-only, and deliberately: a tangent and a reciprocal do not belong in a Q16.16 datapath. Both are evaluated in real and the values convert at the port boundary, which is what the Trigonometry family does for the same reason. The seven software targets are exact.

Simulink bridge

None (Support::None). besself is a MATLAB function, and the one Simulink block that carries a Bessel design – Analog Filter Design, in the DSP System Toolbox – does the design internally and exposes no part of it: it takes a signal in and gives a filtered signal out, so it has no coefficients a diagram could read. There is therefore no library path this block could name. The bridge reports it rather than dropping it silently, and it has no parity testbench; code export verification still covers it across all ten languages. No configuration of it crosses either, including "Sampling Time (s)", which has no counterpart to be written to.

Notes

• Algebraic, with no state: the output depends only on the current input.
• The bilinear transform does not preserve a flat group delay, and no design can make it. The map warps the frequency axis, so the digital filter reported here is flattest in delay near zero frequency and progressively less so towards f_s/2, where the warping is worst. That is why no toolbox offers a digital Bessel design as a single call, and why this block states the limitation rather than implying a property the map cannot carry. Keep f_c well below f_s/4 if the delay is what you came for.
• Highpass keeps the poles and loses the point. A maximally flat group delay is a property of the lowpass prototype; exchanging s and 1/s gives a perfectly good Bessel-derived highpass whose delay is not flat. The option is offered because the mapping is the same one every block in this family uses, not because the result inherits the prototype's virtue.
• The clamp is a live branch, not a safety net. f_c is clamped into (0, f_s/2) by (|x−lo| − |x−hi| + lo + hi)/2, branchless and identical in this block and in all ten emitted bodies, so they agree bit for bit. It exists because VHDL's TAN raises an error at π/2, which stops a simulation rather than returning a bad number. A cutoff at or below zero therefore designs at the bottom of the band rather than failing: T → 0, the numerator collapses and the denominator becomes (z−1)^N. The committed documentation sample shows it at f_c = 0 – every entry of b below 1e−22, against a = [1, −3, 3, −1] to eight digits.
• Measured against R2026a, at f_s = 4 Hz over orders 1 to 8, cutoffs 0.7 Hz and 1.1 Hz and both types, against besself → lp2lp/lp2hp → bilinear: the largest disagreement on any coefficient is 9.7e−15 at order 8, and 8.3e−16 at order 3.
• No state space: one scalar in and two vectors out, so there is no A/B/C/D to merge and model reduction correctly declines it.