Timed Based Linearization — Control Systems/Model Wide Utilities
Control_Systems/Model_Wide_Utilities/Timed_Based_Linearization · 0 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Timed-Based Linearization
Control Systems / Model Wide Utilities
Takes a linear model of the whole diagram at set times during a run:
the state-space matrices a, b, c and d of the diagram
linearized between its input and output gates (as MATLAB's linmod
takes them between a model's root Inports and Outports), at the operating point of
the step it is taken in. When the run ends, each snapshot is left in the
variables space as one record.
Ports
- None. The block is placed anywhere in the diagram; what it linearizes is the whole diagram, between the input and output gates of the top level.
Parameters
- Linearization Time – the times, in seconds, a snapshot is taken at: one number or a vector. Under a fixed step a snapshot is taken on the first step at or after each time (a time of 0 is taken at the first step after the start), two times inside one step give one snapshot, and a time before the start or after the stop gives none. Under a variable step the solver steps exactly onto each time. Default 1.
- Linearization Sample Time – the
Tswritten into the result. 0, the default, is the continuous linearization (linmod). A positive value asks for MATLAB's discrete linearization (dlinmod), which ICore does not compute; it is refused. - Sampling Time (s) – not used: the block takes its snapshots at the times above. It does not cross to Simulink.
What the run leaves
One record per snapshot, in time order, named from the block's path with every
character that is not a letter, a digit or _ made _, as
Simulink names its variable: a block T L on the top level gives
Home_T_L, then Home_T_L_2, Home_T_L_3, and
so on. Each holds a, b, c, d,
the operating point as OperPoint_x (the states, a column),
OperPoint_u (the inputs, a row) and OperPoint_t, and
Ts. Simulink's StateName, OutputName and
InputName are cells of block paths, and a record here holds numbers
only, so reading one says so by name.
When nothing is left
A snapshot needs the Continuous solver with Joint coupling, where ICore integrates the whole diagram as one system. Under any other the run warns once, with the reason, and leaves nothing; so does a run in which no time is reached.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, as a named body that does nothing: a linearization is an analysis of the live run.
Simulink bridge
Import and export, mapped to simulink/Model-Wide Utilities/Timed-Based
Linearization: Linearization Time ↔
LinearizationTime and Linearization Sample Time ↔
SampleTime.
Notes
- The matrices are central differences of the joint step: against Simulink's
analytic
linmodthey agree within about 1e-7, and the operating point exactly. - To take a snapshot on an event instead of at a time, use Model-Wide Utilities / Trigger-Based Linearization.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Model_Wide_Utilities/Timed_Based_Linearization |
| family | Control_Systems/Model_Wide_Utilities |
| solver environment class | ICoreBlock_0_Control_Systems_1_Model_Wide_Utilities_2_Timed_Based_Linearization |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Model_Wide_Utilities/Timed_Based_Linearization/ICoreBlock_0_Control_Systems_1_Model_Wide_Utilities_2_Timed_Based_Linearization.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Model_Wide_Utilities/Timed_Based_Linearization/ICoreBlock_0_Control_Systems_1_Model_Wide_Utilities_2_Timed_Based_Linearization.h |
| default size on canvas | 80 × 80 px |
| ports at insert | 0 in, 0 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
The constructor creates no port explicitly — the port list comes from registerInitialPorts (0 in, 0 out) or from the block's configuration.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Linearization Time | 1 | LinearizationTime |
Linearization Sample Time | 0 | SampleTime |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Model-Wide\nUtilities/Timed-Based\nLinearization |
| port-count rule | PortsParam:: |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Linearization Time | LinearizationTime | passes through |
Linearization Sample Time | SampleTime | passes through |
Caveat (shown to the user): the mask's SampleTime is the RESULT's Ts, not a rate, so it crosses as Linearization Sample Time and the block's own rate does not cross
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Timed-Based Linearization -- the whole diagram linearized at set times during a run Measured on R2026a (FEATURES_TO_ADD.md §F.BF17, BF17.1): a masked subsystem over
sfunlin, library pathsimulink/Model-Wide\nUtilities/Timed-Based\nLinearization, no ports, two parameters:LinearizationTime(default 1, may be a vector) andSampleTime(default 0, the result's Ts; 0 islinmod, a positive onedlinmod). Under a fixed step it fires on the first major step at or after each time (T = 0 fires at h; two times inside one step give one snapshot; a time before the start or past the stop gives none); under a variable step the solver lands on each time. It writes a struct array, one element per snapshot, named from the block's path. Checked against R2026a's own block on a pendulum (BF17.5): the same snapshot times, the state to 1e-12, A, B, C, D within 1e-7. The timing and the record are ICoreRunLinearization's; the rest is ICoreLinearizationBlockBase.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.