Model Info — Control Systems/Model Wide Utilities

Control_Systems/Model_Wide_Utilities/Model_Info · 0 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Model Info

Control Systems / Model Wide Utilities

A stamp: a short template whose %<tags> are replaced with facts about the model this block sits in. The result is shown on the block's face and carried into the generated code as a comment. It has no ports and computes nothing.

Ports

None. Not one input, not one output.

How it differs from DocBlock

DocBlock carries text you wrote, exactly as you wrote it. This block carries text the MODEL fills in – so a stamp on an exported core says which solver, which rate and which horizon it was generated for, and stays right when those change.

The tags

Every tag below names something this tree actually has. An unknown tag is left in the text exactly as typed, and reported by name when the run starts, so a misspelling shows up rather than silently becoming blank.

The diagram – %<diagram> (the name of the subsystem level this block sits on), %<path> (this block's full path).
The solver – %<solver>, %<stepping>, %<fixedstep> (yes/no), %<coupling>, %<discretization>.
Rates and horizon – %<sampletime> (the global rate), %<starttime>, %<stoptime> (which reads infinite on an endless run), %<maxstep>, %<minstep>, %<initialstep>.
Tolerances – %<reltol>, %<abstol>.
When it was rendered – %<date>, %<time>. See the warning below before putting these in a template you export.

⚠ %<date> and %<time> make an export non-reproducible. They are substituted when the text is rendered, so a core exported twice from an unchanged model differs on those lines and every diff of generated code shows them. They are offered because a stamp is what this block is for – but a model that needs byte-identical exports should leave them out of the template.

Parameters

Text – the template, edited in the code editor so it can run to many lines. Line breaks are kept.
Show On Face – on paints the rendered text on the block, off keeps it in the dialog only.
Emit In Generated Code – on writes the rendered text into every exported target as a comment.
Sampling Time (s) – present on every block, and inert here: this block does nothing per step.

Code export

All ten targets, as comments in each one's own syntax: Python (#), MATLAB (%), Java, C, C++, Rust, Verilog, SystemVerilog (//), VHDL (--) and PLC Structured Text ((* … *)). The tags are substituted BEFORE the comment is built, so the exported core carries the facts rather than the template.

⚠ PLC Structured Text has the rendered text neutralised, as DocBlock's does: (* … *) is its only comment form, so a *) anywhere in the text would close the comment early and leave the rest as ST source. Any *) is emitted as * ).

With Emit In Generated Code off the block still emits its (empty) function – an empty body would abort the whole model's export, not just skip this block.

Code-export verification

Excluded from the code-export verification matrix, by name, in ICoreParityRigLibrary::unriggableTypes(): no ports and nothing computed, so there is no signal to record or compare on either side.

Simulink bridge

None, and the vocabulary is the reason rather than the mechanism. Measured on R2026a: Simulink's Model Info is a masked SubSystem (MaskType=CMBlock), ZERO ports, no SampleTime, VIRTUAL, OpenFcn = slcm and MaskSelfModifiable = on – it rewrites its own mask display from DisplayStringWithTags. Its tags name a configuration-management vocabulary, every entry of which was confirmed present as a model parameter: ModelVersion, Creator, LastModifiedBy, Created, LastModifiedDate, Description. An ICore diagram has none of them – no version, no author, no revision history – so a faithful copy of that tag list would substitute blanks. This block keeps the mechanism and substitutes a vocabulary this tree actually has, which makes it a DIFFERENT block rather than a mapping of Simulink's, and it is reported on exchange rather than asserted.

Notes

The text is rendered once per run, when the block's configuration is loaded: every tag names a fact that is fixed for the run, so nothing is substituted per step.
An unknown tag is a warning, not an error. The run starts, the tag stays in the text as typed, and the log names it: "Model Info: unknown tag(s) %<name> at <path>. They are left in the text as typed". It is reported with Show On Face off too.
Text is a template, never an expression: it is not resolved from the variables space.
The dialog does not let you add a port, and a Model Info block that somehow carries one refuses to run: "Invalid number of ports at Model Info block: <path>. A Model Info block has no ports at all."

Code facts#

Fact	Value
registered type	`Control_Systems/Model_Wide_Utilities/Model_Info`
family	`Control_Systems/Model_Wide_Utilities`
solver environment class	`ICoreBlock_0_Control_Systems_1_Model_Wide_Utilities_2_Model_Info`
source	`src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Model_Wide_Utilities/Model_Info/ICoreBlock_0_Control_Systems_1_Model_Wide_Utilities_2_Model_Info.cpp`
header	`src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Model_Wide_Utilities/Model_Info/ICoreBlock_0_Control_Systems_1_Model_Wide_Utilities_2_Model_Info.h`
default size on canvas	150 × 70 px
ports at insert	0 in, 0 out
code generators implemented	`Python`, `MATLAB`, `Java`, `Rust`, `C`, `C++`, `VHDL`, `Verilog`, `SystemVerilog`, `PLC Structured Text`

Ports#

The constructor creates no port explicitly — the port list comes from registerInitialPorts (0 in, 0 out) or from the block's configuration.

Configuration variables#

Config variable	Default	Simulink parameter
`Text`	`DEFAULT_TEXT`	—
`Show On Face`	`on%~%off~~on`	—
`Emit In Generated Code`	`on%~%off~~on`	—

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

Simulink bridge#


support	`Support::None`
Simulink path	—
port-count rule	`PortsParam::None`
`SampleTime` parameter	yes

Caveat (shown to the user): Simulink's Model Info is a masked SubSystem (MaskType=CMBlock) with ZERO ports of any kind, no SampleTime, VIRTUAL, OpenFcn = slcm and MaskSelfModifiable = on - measured on R2026a. The MECHANISM matches this block (a template whose tags are substituted at render time) but the VOCABULARY does not and cannot: Simulink's tags name configuration-management facts - ModelVersion, Creator, LastModifiedBy, Created, LastModifiedDate, Description, every one confirmed present as a model parameter - and an ICore diagram carries no version, no author and no revision history, so a faithful copy of that tag list would substitute blanks. This block substitutes a vocabulary this tree actually has instead (the solver configuration, the rates, the horizon, the tolerances), which makes it a DIFFERENT block rather than a mapping of Simulink's, and it is reported on exchange rather than asserted

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:

B0 no sample under docs/generated/samples/ — nothing to cross-check (P8.1)

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Model Info -- a stamp whose %<tags> are replaced with facts about the model Zero ports, no state, no arithmetic. "Text" is a template; every %<tag> in it is replaced with a model or solver fact; the result goes on the block's face and into the generated code as a comment.

⚠ THE MECHANISM IS SIMULINK'S AND THE VOCABULARY IS NOT, which is the whole finding on this row. Measured on R2026a (2026-09-17): Simulink's Model Info is a masked SubSystem, MaskType=CMBlock, ZERO ports, no SampleTime, VIRTUAL, OpenFcn = slcm (Simulink configuration management) and MaskSelfModifiable = on -- it rewrites its own MaskDisplayString from DisplayStringWithTags. Its tags come from a CONFIGURATION-MANAGEMENT vocabulary, and every one was confirmed present as a model parameter: ModelVersion (1.0), Creator, LastModifiedBy, Created, LastModifiedDate, Description.

THIS TREE HAS NONE OF THOSE. An ICore diagram carries no version, no author and no revision history, so copying that tag list would substitute blanks and the block would be empty -- which is exactly why this row was released back to open once before being built.

What this tree HAS is what those models mostly do not put on the canvas: the SOLVER CONFIGURATION the diagram will actually run under. ICoreModelConfigurator exposes all of it statically. So the template stays and the vocabulary is replaced with one where every tag names something that exists -- and the block is honest about being a different block.

⚠ %<date> AND %<time> MAKE AN EXPORT NON-REPRODUCIBLE: substituted when the text is rendered, so a core exported twice from an unchanged model differs on those lines. Offered because a stamp is what this block is for; said plainly in the description rather than left to be discovered by a diff.

Sample results#

No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.