Check Static Range — Control Systems/Model Verification

Check Static Range

Control Systems / Model Verification

Verifies that a signal stays INSIDE a constant band, and publishes the verdict as a signal: y = 1 where the entry passes, y = 0 where it fails. The test is min ≤ u ≤ max, with each end turned strict independently by its own inclusion flag. Applied entry by entry, so a matrix signal is checked element for element.

Ports

• Input – the signal u under test, of any size [m,n].
• Output – the verdict y, of the SAME size [m,n]: one 1.0/0.0 flag per entry of u. The block never reshapes a signal.

Parameters

• Minimum – scalar, the bottom of the band. Defaults to 0, as in Simulink.
• Include Minimum – whether a sample sitting exactly ON the bottom passes.
  • on – the lower test is u ≥ min (the default).
  • off – the lower test is u > min.
• Maximum – scalar, the top of the band. Defaults to 100, as in Simulink.
• Include Maximum – whether a sample sitting exactly ON the top passes.
  • on – the upper test is u ≤ max (the default).
  • off – the upper test is u < max.
• Enabled – whether a failing sample is REPORTED. It does not change the output signal: an entry that fails still reads 0 with this off, which is what Simulink's counterpart does.
  • on – a failure is logged once per run, with the block's path and the time it first happened (the default).
  • off – the block computes its verdict silently.
• Stop When Assertion Fails – whether a reported failure also ends the run.
  • on – the run stops at the first failing sample and is marked failed (the default).
  • off – the run continues and the failure is a warning.
  Ignored entirely when Enabled is off.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Both bounds are scalars; a per-entry band sized like the input is not implemented and is reported rather than broadcast from its first entry. For a band that varies over time, use Check Dynamic Range, which takes both ends on ports.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Both bounds and both comparisons are baked into the generated code at export time rather than exposed as tunable parameters, matching the other comparison blocks. Only the VERDICT SIGNAL is exported: Enabled and Stop When Assertion Fails have no meaning in a deployed core, which has no simulation to stop, so a core computes the flag and leaves acting on it to whatever consumes the signal.

Simulink bridge

Import and export, mapped to simulink/Model Verification/Check Static Range. "Minimum" to min, "Include Minimum" to min_included, "Maximum" to max, "Include Maximum" to max_included, "Enabled" to enabled and "Stop When Assertion Fails" to stopWhenAssertionFail, all as plain pass-through values, so the round trip is lossless. The block always sets Simulink's export to on: ICore's block always has its verdict output, whereas Simulink's grows one only when that box is ticked, so importing a block with it unticked reports the difference rather than silently dropping the port. The Simulink counterpart has no SampleTime parameter, so "Sampling Time (s)" does not cross – the block runs at the surrounding Simulink rate.

Notes

• Algebraic, with no signal state. The only state is a one-shot latch so that a failing run logs its complaint once rather than once per sample.
• Not linear, and so deliberately carries no state space – model reduction reports it as unmergeable rather than absorbing a comparison.
• An INVERTED band (min above max) is not an error: no sample can satisfy both ends at once, so every entry simply fails. That is Simulink's behaviour too.
• For the complement – a band the signal must AVOID – use Check Static Gap, which is this block's mirror image.