Check Dynamic Gap — Control Systems/Model Verification
Control_Systems/Model_Verification/Check_Dynamic_Gap · 3 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Check Dynamic Gap
Control Systems / Model Verification
Verifies that a signal stays strictly OUTSIDE a band whose two ends are themselves signals – the mirror image of Check Dynamic Range – and publishes the verdict: y = 1 where the entry passes, y = 0 where it fails. The test is u < min or u > max, taken entry by entry, with all three operands read at the same step – so the forbidden gap may move every sample.
Ports
- max (input 1) – the moving TOP of the forbidden gap.
- min (input 2) – the moving BOTTOM of the forbidden gap.
- u (input 3) – the signal under test.
- Output – the verdict y, the SAME size as u: one 1.0/0.0 flag per entry.
The order is max, min, u – the two bounds first and the signal LAST, which is Simulink's order and not the one the labels suggest. It was established by driving the real block rather than read off its mask, which is empty. All three inputs must be the same size [m,n]; a scalar bound is not broadcast against a wider signal, and a mismatch is reported rather than guessed at.
Parameters
- Enabled – whether a failing sample is REPORTED. It does not
change the output signal: an entry that fails still reads 0 with this off, which
is what Simulink's counterpart does.
- on – a failure is logged once per run, with the block's path and the time it first happened (the default).
- off – the block computes its verdict silently.
- Stop When Assertion Fails – whether a reported failure also ends
the run.
- on – the run stops at the first failing sample and is marked failed (the default).
- off – the run continues and the failure is a warning.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
There are deliberately no bound parameters and no inclusion flags: both ends arrive on ports, and both comparisons are always strict. For constant ends, or to choose whether the boundaries themselves pass, use Check Static Gap – where, note, the inclusion flags read the opposite way round.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Nothing is inlined as a constant – all three operands are signals – so the generated body is a pair of comparisons and the block has no tunable parameters. Only the VERDICT SIGNAL is exported: Enabled and Stop When Assertion Fails have no meaning in a deployed core, which has no simulation to stop.
Simulink bridge
Import and export, mapped to simulink/Model Verification/Check Dynamic
Gap. "Enabled" to enabled and "Stop When Assertion Fails" to
stopWhenAssertionFail, both as plain pass-through values, so the
round trip is lossless. The block always sets Simulink's export to
on: ICore's block always has its verdict output, whereas Simulink's
grows one only when that box is ticked. The Simulink counterpart has no
SampleTime parameter, so "Sampling Time (s)" does not cross –
the block runs at the surrounding Simulink rate.
Notes
- Algebraic, with no signal state. The only state is a one-shot latch so that a failing run logs its complaint once rather than once per sample.
- Not linear, and so deliberately carries no state space – model reduction reports it as unmergeable rather than absorbing a comparison.
- An INVERTED gap (min above max) is not an error: every sample then clears at least one side, so every entry simply passes. Nothing checks that the two bound signals stay in order, and Simulink does not either.
- For the complement – a moving band the signal must stay INSIDE – use Check Dynamic Range, which shares this block's port order.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Model_Verification/Check_Dynamic_Gap |
| family | Control_Systems/Model_Verification |
| solver environment class | ICoreBlock_0_Control_Systems_1_Model_Verification_2_Check_Dynamic_Gap |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Model_Verification/Check_Dynamic_Gap/ICoreBlock_0_Control_Systems_1_Model_Verification_2_Check_Dynamic_Gap.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Model_Verification/Check_Dynamic_Gap/ICoreBlock_0_Control_Systems_1_Model_Verification_2_Check_Dynamic_Gap.h |
| default size on canvas | 80 × 80 px |
| ports at insert | 3 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | max |
| 2 | in | ICoreDouble | min |
| 3 | in | ICoreDouble | u |
| 4 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Enabled | on%~%off~~on | enabled |
Stop When Assertion Fails | on%~%off~~on | stopWhenAssertionFail |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Model Verification/Check Dynamic Gap |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | export = on |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Enabled | enabled | passes through |
Stop When Assertion Fails | stopWhenAssertionFail | passes through |
Caveat (shown to the user): the band arrives on ports (max, min, u); the block runs at the surrounding Simulink rate, so "Sampling Time (s)" does not cross. ICore's block always carries its verdict output, so the bridge pins Simulink's "export" to on
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0every stimulus in the sample errored — cross-checks skipped
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Check Dynamic Gap -- verifies a signal stays OUTSIDE a band that arrives on ports y = 1 where u < min or u > max, 0 elsewhere. Both ends are SIGNALS, so the band may move every step. Applied entry by entry, so the output keeps the signal port's size.
PORT ORDER IS (max, min, u). NOT (max, u, min), which is what the port labels suggest and what every reasonable person guesses. It was measured: all six permutations of three distinguishable signals were driven through the real R2026a block, and only this one reproduces all six observations. Get it wrong and the block still runs, still produces a plausible-looking 1/0 signal, and is wrong on every sample.
Both ends are STRICT, with no inclusion flags -- also measured, at samples where the signals are exactly equal.
The verdict SIGNAL and the ASSERTION are two separate things, and only the first crosses into generated code -- see Check Static Lower Bound, which documents the split in full.
Sample results#
No stimulus produced a sampled output in this rig — Check Dynamic Gap failed at t = 0.000000 s: ICore Blocks/Home/Check Dynamic Gap. That is a fact about the single-block rig, not a verdict on the block: an offline batch fit, a block whose output only appears at onSolverFinish, or one that needs a driven environment cannot be exercised alone.
Category unsampled · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60
Sample data: docs/generated/samples/Control_Systems__Model_Verification__Check_Dynamic_Gap.json