Receive — Control Systems/Messages And Events
Control_Systems/Messages_And_Events/Receive · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Receive
Control Systems / Messages And Events
Reads messages: on each of its sample hits it takes one message from the message line into its input and outputs the value v it carries. A message taken is consumed. On a hit with no message waiting, v holds the value of the last message taken – or reads the Initial value, by the Value source when queue is empty – and before the first message it reads the Initial value either way.
Ports
- Input msg – a message line, from a Send or another block that sends messages; its messages are any size [m,n], or a bus (a Hit Crossing Probe’s).
- Output status – only with Show queue status On, and then the first output, as in Simulink: a boolean, 1 on a hit that took a message and 0 on one that found none.
- Output v – the value, the size of the messages; the second output
when the status is shown. When the messages are a bus, v is that bus
(
bus), element for element, for a Bus Selector to read.
Parameters
- Use internal queue – Off (default): the block keeps one message, and a newer one overwrites it, so a reader slower than its sender reads the newest. On: it keeps a queue, as the next three set.
- Queue overwriting – with the queue on: On (default) drops the oldest message when a new one arrives at a full queue; Off drops the new one, and the run reports how many were dropped, as R2026a warns.
- Queue length – with the queue on: how many messages it keeps, a whole number of at least 1. Default 1.
- Queue type – with the queue on, which message is taken first:
- LIFO (default) – the newest.
- FIFO – the oldest.
- Priority – refused: it orders messages by a field of a bus message, which ICore’s queues do not read.
- Priority order – Ascending (default) or Descending; read only by a Priority queue, so it has no effect here.
- Show queue status – Off (default): one output, v. On: two, the status then v. The output count must agree: add or remove the port to match, or the run is refused with the block’s name.
- Initial value – what v reads before the first message: a scalar,
broadcast, or a matrix the size of the messages.
[], the default, reads 0. With bus messages only 0 or[], which zero every element; any other value is refused, as R2026a refuses it. - Value source when queue is empty – Hold last value (default) or Use initial value.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
Python, MATLAB, Java, Rust, C and C++: the message line is one fixed-capacity queue in the generated core, held beside the signals, and it keeps its reader’s policy (a Receive’s queue, or a message-triggered subsystem’s). Each call pops the line’s queue: a message replaces the value held and sets the status, and with none the value holds or reads the Initial value, as live. A bus message rides the queue as its elements’ numbers in order, and v is the bus record built from them.
VHDL, Verilog, SystemVerilog and PLC Structured Text refuse a message line by name: a hardware queue is left until a hardware design asks for one. A message line that crosses the boundary of the subsystem being exported is refused by every target.
Simulink bridge
Import and export, mapped to simulink/Messages & Events/Receive.
Use internal queue ↔ UseInternalQueue, Queue
overwriting ↔ QueueOverwriting and Show queue status
↔ ShowQueueStatus (Off/On ↔ off/on), Queue length
↔ QueueLength, Queue type ↔ QueueType
and Priority order ↔ PriorityOrder (one value for one
value), Initial value ↔ InitialValue, Value source when
queue is empty ↔ ValueSourceWhenQueueIsEmpty, and
"Sampling Time (s)" ↔ SampleTime, as on every block.
Simulink moves the status port itself.
Notes
- Stateful: it keeps the messages waiting and the last value taken.
- Measured on R2026a: a Hit Crossing Probe into a Receive gives its
HitCrossMessage bus, with
[]or 0 as the Initial value; -9 is refused (BusParameterMustBeZeroOrStruct). - Measured on R2026a: a Send every 0.25 s into a Receive every 1 s with no queue reads 100, 101, 102 (the newest); with a FIFO queue of 3, 100, 100.5, 101.5, 102.5; with a FIFO queue of 2 and overwriting off, 100, 100.25, 100.5, 101.25, 102.25, and 11 messages dropped.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Messages_And_Events/Receive |
| family | Control_Systems/Messages_And_Events |
| solver environment class | ICoreBlock_0_Control_Systems_1_Messages_And_Events_2_Receive |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Messages_And_Events/Receive/ICoreBlock_0_Control_Systems_1_Messages_And_Events_2_Receive.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Messages_And_Events/Receive/ICoreBlock_0_Control_Systems_1_Messages_And_Events_2_Receive.h |
| default size on canvas | 60 × 60 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++ |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreMessage | msg |
| 2 | out | ICoreDouble | v |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Use internal queue | Off%~%On~~Off | UseInternalQueue |
Queue overwriting | Off%~%On~~On | QueueOverwriting |
Queue length | 1 | QueueLength |
Queue type | FIFO%~%LIFO%~%Priority~~LIFO | QueueType |
Priority order | Ascending%~%Descending~~Ascending | PriorityOrder |
Show queue status | Off%~%On~~Off | ShowQueueStatus |
Initial value | [] | InitialValue |
Value source when queue is empty | Hold last value%~%Use initial value~~Hold last value | ValueSourceWhenQueueIsEmpty |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Messages\n& Events/Receive |
| port-count rule | PortsParam::ReceiveStatusPort |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Use internal queue | UseInternalQueue | Off → off, On → on |
Queue overwriting | QueueOverwriting | Off → off, On → on |
Queue length | QueueLength | passes through |
Queue type | QueueType | FIFO → FIFO, LIFO → LIFO, Priority → Priority |
Priority order | PriorityOrder | Ascending → Ascending, Descending → Descending |
Show queue status | ShowQueueStatus | Off → off, On → on |
Initial value | InitialValue | passes through |
Value source when queue is empty | ValueSourceWhenQueueIsEmpty | Hold last value → Hold last value, Use initial value → Use initial value |
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 3 entries for 2 ports (1 in, 1 out), and the 3 they cover does not reconcile — grouped, or one undocumented? a reader must sayB0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.