Hit Crossing Probe — Control Systems/Messages And Events
Control_Systems/Messages_And_Events/Hit_Crossing_Probe · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Hit Crossing Probe
Control Systems / Messages And Events
Sends a message for every element of u that crosses, reaches or leaves an offset. With s the sign of u − offset (−1, 0 or +1) and sp its value at the previous sample hit, an element whose s differs from sp sends one message whose CrossingType names the pair: −+ 1, −0 2, 0+ 4, +− 8, +0 16, 0− 32. On the first sample an element sitting on the offset sends None (0), and one off it sends nothing. Leaving the offset in the direction it arrived from is not sent (0+ just after −0, 0− just after +0), so a one-sample touch is one crossing.
Ports
- Input u – the signal watched, any size [m,n]; every element is watched on its own.
- Output msg (
msg) – a message line. Each message is a bus, R2026a's HitCrossMessage, of four elements: CrossingType (i32), the code above; Index (u32), the element that crossed, counted from 1 down the columns; Time, the sample hit; and Offset, the offset. Messages of one hit go out in element order. Read them with a Receive, whose value is then that bus.
Parameters
- Hit Crossing Offset – the offset, a scalar. Default 0.
- Hit Crossing Direction – which crossings are sent:
- either (default) – every one, and the first sample’s None.
- rising – −+, −0 and 0+.
- falling – +−, +0 and 0−.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
Python, MATLAB, Java, Rust, C and C++: the message line is one fixed-capacity queue in the generated core, and each crossing is pushed onto it as the bus’s four numbers, which the Receive at the other end turns back into the bus. The offset and the direction are inlined; the previous sign and crossing of every element are the block’s state, and Time is the block’s own clock.
VHDL, Verilog, SystemVerilog and PLC Structured Text refuse a message line by name: a hardware queue is left until a hardware design asks for one.
Simulink bridge
Import and export, mapped to simulink/Messages & Events/Hit Crossing
Probe. Hit Crossing Offset ↔ HitCrossingOffset,
Hit Crossing Direction ↔ HitCrossingDirection (either,
rising, falling, one value for one value), and "Sampling Time (s)" ↔
SampleTime, as on every block. The export sets
HitCrossingOutputType Message and ShowOutputPort on; a
Discontinuities Hit Crossing whose HitCrossingOutputType is Message
imports as this block. CrossingType is R2026a’s
slHitCrossingType enumeration in Simulink and its int32 value here.
Notes
- Stateful: one previous sign and one previous crossing per element.
- Measured on R2026a, offset 0.25, either, at 0.1 s: u = 0.25 0.25 1 0.25 −1 0.25 0.25 1 sends None at 0, 0+ at 0.2, +0 at 0.3, −0 at 0.5 and 0+ at 0.7 – and nothing at 0.4, the second half of the touch at 0.3.
- Time is the sample hit, also under a continuous solver: R2026a reports the step after a crossing, not an interpolated instant, at a fixed step.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Messages_And_Events/Hit_Crossing_Probe |
| family | Control_Systems/Messages_And_Events |
| solver environment class | ICoreBlock_0_Control_Systems_1_Messages_And_Events_2_Hit_Crossing_Probe |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Messages_And_Events/Hit_Crossing_Probe/ICoreBlock_0_Control_Systems_1_Messages_And_Events_2_Hit_Crossing_Probe.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Messages_And_Events/Hit_Crossing_Probe/ICoreBlock_0_Control_Systems_1_Messages_And_Events_2_Hit_Crossing_Probe.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++ |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreMessage | msg |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Hit Crossing Offset | 0 | HitCrossingOffset |
Hit Crossing Direction | either%~%rising%~%falling~~either | HitCrossingDirection |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Messages\n& Events/Hit Crossing Probe |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | ShowOutputPort = on, HitCrossingOutputType = Message |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Hit Crossing Offset | HitCrossingOffset | passes through |
Hit Crossing Direction | HitCrossingDirection | either → either, rising → rising, falling → falling |
Caveat (shown to the user): The CrossingType element is R2026a's slHitCrossingType enumeration in Simulink and its int32 value in ICore: a bus element names no enumeration type.
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.