Generated reference › Submatrix — Control Systems/Matrix Operations
kind: generated#block#control-systems-matrix-operations

Submatrix — Control Systems/Matrix Operations

Control_Systems/Matrix_Operations/Submatrix · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Submatrix

Control Systems / Matrix Operations

Passes a rectangular window of the input through and drops the rest: y = u(r1:r2, c1:c2). The rows and the columns are selected independently, each by a span and, where the span needs them, a start and an end anchor. Nothing is scaled and no element is combined with another.

Ports

  • Input – the matrix u, of any size [m,n]. The window is resolved against this size, so a range that reaches past it is reported when the model is built rather than clipped.
  • Output – the selected window, [r2−r1+1, c2−c1+1]. Its size follows from the parameters and the input's size together; both ends are inclusive.

Parameters

Ten in all, five per dimension, and the two dimensions work identically.

  • Row Span – which rows are considered at all:
    • All rows – every row; both row anchors are ignored.
    • One row – a single row, at the START anchor. The end anchor is ignored.
    • Range of rows – from the start anchor to the end anchor, inclusive. This is the default, as in Simulink.
  • Row Start Mode – where the range begins, on a dimension of size n:
    • First – row 1. The default.
    • Index – the row named by Row Start Index, counting from 1.
    • Offset from last – n − the index, so an index of 0 is the last row itself.
    • Last – row n.
    • Middle – row floor(n/2)+1, which is the upper of the two middles when n is even.
    • Offset from middle – that middle plus the index.
  • Row Start Index – the whole number the three indexed modes above read. Ignored by First, Last and Middle. Under Index it must be 1 or more; under the two offset modes 0 or more.
  • Row End Mode – where the range ends. The same list without First, exactly as Simulink's dialog has it, and defaulting to Last.
  • Row End Index – the whole number the end's indexed modes read.
  • Column Span, Column Start Mode, Column Start Index, Column End Mode, Column End Index – the same five over the columns, with All columns / One column / Range of columns in place of the row spellings.
  • Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

A window that would start before the first element, end past the last, or end before it starts is reported when the model is built; the block does not clip silently.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Because both ranges are config, the whole window is resolved at export time and the copy is unrolled: no span or anchor branch survives into the generated core, and nothing is tunable on it.

The three HDL targets are fully synthesizable. Selecting a window is pure data movement, so the values stay in the Q16.16 datapath and nothing is converted at the port boundary or approximated.

Simulink bridge

Import and export, mapped to simulink/Matrix Operations/Submatrix. All ten parameters cross, one for one, and every combo value is spelled here exactly as Simulink spells it, so the translation is lossless in both directions: "Row Span" → RowSpan, "Row Start Mode" → RowStartMode, "Row Start Index" → RowStartIndex, "Row End Mode" → RowEndMode, "Row End Index" → RowEndIndex, and the five column parameters onto ColSpan, ColStartMode, ColStartIndex, ColEndMode and ColEndIndex.

The Simulink block defines no SampleTime parameter, so the rate is not carried across: it stays on the ICore side, and a block configured with an explicit positive rate reports that the rate did not cross.

Notes

  • Algebraic, with no state – pure signal reindexing.
  • Deliberately carries no state space, even though selecting a window is linear: it reshapes, and a D matrix can rescale a signal but never re-index one.
  • The Middle anchor takes the UPPER middle on an even dimension – floor(n/2)+1, so column 3 of 4 – which is what Simulink does and is worth knowing before relying on it.

Code facts#

FactValue
registered typeControl_Systems/Matrix_Operations/Submatrix
familyControl_Systems/Matrix_Operations
solver environment classICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Submatrix
sourcesrc/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Submatrix/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Submatrix.cpp
headersrc/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Submatrix/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Submatrix.h
default size on canvas100 × 70 px
ports at insert1 in, 1 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDouble
2outICoreDouble

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Row SpanAll rows%~%One row%~%Range of rows~~Range of rowsRowSpan
Row Start ModestartModes~~FirstRowStartMode
Row Start Index1RowStartIndex
Row End ModeendModes~~LastRowEndMode
Row End Index1RowEndIndex
Column SpanAll columns%~%One column%~%Range of columns~~Range of col…ColSpan
Column Start ModestartModes~~FirstColStartMode
Column Start Index1ColStartIndex
Column End ModeendModes~~LastColEndMode
Column End Index1ColEndIndex

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::Both
Simulink pathsimulink/Matrix Operations/Submatrix
port-count rulePortsParam::None
SampleTime parameterno — the counterpart defines none; the rate stays on the ICore side
ICore configSimulink parameterValue translation
Row SpanRowSpanpasses through
Row Start ModeRowStartModepasses through
Row Start IndexRowStartIndexpasses through
Row End ModeRowEndModepasses through
Row End IndexRowEndIndexpasses through
Column SpanColSpanpasses through
Column Start ModeColStartModepasses through
Column Start IndexColStartIndexpasses through
Column End ModeColEndModepasses through
Column End IndexColEndIndexpasses through

Caveat (shown to the user): all ten parameters cross one for one, and the combo values are spelled here exactly as Simulink spells them, so the mapping needs no translation table and is lossless both ways; the index parameters a span or a mode does not consult still cross, which is also what Simulink stores

Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Submatrix -- a rectangular window of the input, selected by config alone Both ranges are dialog parameters; nothing arrives on a port. So the window is resolved once at model-build time and the block becomes an unrolled copy, which is what lets all ten targets emit a straight-line body with no index arithmetic in it.

THE INDEX MODES were measured against Simulink R2026a on a 5x4 lattice whose entries encode 10*row + column, so every pick is identifiable. For a dimension of size N and a dialog index k:

First 1 Index k (k >= 1; Simulink rejects 0 outright) Offset from last N - k (k = 0 is the last element itself) Last N Middle floor(N/2) + 1 (3 for N = 5 and for N = 4; 2 for N = 3) Offset from middle floor(N/2) + 1 + k

HDL is SYNTHESIZABLE: a window is pure data movement, so the values stay in the Q16.16 datapath and nothing is converted at the port boundary.

Algebraic and stateless. No state space -- see the header for why.

Sample results#

Submatrix — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sampleSubmatrix — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample-202-2-10123inputoutput
tin ICoreDouble-Out-0out ICoreDouble-Out-0
0-2-2
0.40.50.5
0.8-2-2
1.20.50.5
1.6-2-2
20.50.5
2.4-2-2
2.80.50.5
3.2-2-2
3.60.50.5
4-2-2
4.40.50.5
4.8-2-2
5.20.50.5

Every 4th of 60 samples, from the table stimulus.

The same rig also ran:

StimulusWhat it isOutput range
impulseImpulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair)0 … 1
rampRamp: slope 1 from t = 00 … 5.8
sineSine Wave: amplitude 1, 2 rad/s, no phase, no bias-1 … 0.9996
stepStep: 0 -> 1 at t = 1 s0 … 1

Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample

Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Matrix_Operations__Submatrix.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).