Permute Matrix — Control Systems/Matrix Operations
Control_Systems/Matrix_Operations/Permute_Matrix · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Permute Matrix
Control Systems / Matrix Operations
Re-emits the input's rows – or its columns – in the order named by a second input P: y = u(P, :) or y = u(:, P). Because P is a live signal and may repeat an index or leave one out, the output's size follows P's length, not the input's.
Each index is floored, shifted by one if the base is zero, and then clipped into the valid range – so an index of 0 or 9 on a three-column input selects column 1 or column 3 rather than failing.
Ports
- u – the matrix, of any size [m,n].
- P – the index vector, of any length L. It may be a row [1,L] or a column [L,1]; anything else is reported when the model is built. Its VALUES are read every sample, so the order can change during a run.
- Output – [L,n] when permuting rows, [m,L] when permuting columns. L is the only thing P contributes to the size; its values decide only which row or column lands where.
Parameters
- Permute – which dimension is reordered:
- Columns – the columns, so P names columns and the output has L of them. This is the default, as in Simulink.
- Rows – the rows, so P names rows and the output has L of them.
- Index Base – how P's values are read:
- One-based – 1 selects the first row or column. The default.
- Zero-based – 0 selects the first.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Out-of-range indices are always clipped. Simulink also offers "Clip and warn" and "Generate error"; ICore implements neither, and the bridge pins the Simulink setting to plain clipping rather than pretending otherwise – a model carrying one of the other two is reported on import.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The axis and the index base are resolved at export time, so neither branch survives into the generated core; the floor, the clamp and the lookup are what remain, and they run per sample because P does.
The three HDL targets are fully synthesizable. The index is recovered
with fx_to_int, an arithmetic shift right that is exactly the
floor() the software targets use, and the clamped result addresses
the input directly – which synthesizes to a multiplexer.
The HDL targets receive P already quantized, to a Q16.16 grid whose quantum is 1.5×10-5. Flooring is a step function, so a P element sitting within one quantum of a whole number can floor to a different index there than in the software targets – and a wrong index moves a whole row or column rather than nudging a value. Drive P with whole numbers and the HDL cores are bit-exact; derive it from a continuous signal and they are not.
Simulink bridge
Import and export, mapped to simulink/Matrix Operations/Permute
Matrix. "Permute" → mode and "Index Base" →
ZeroOneIdxMode, both spelled here exactly as Simulink spells them,
so the translation is lossless in both directions. The entry also always writes
errmode = Clip index and checkDims =
off, which is what this block does.
The Simulink block defines no SampleTime parameter, so the
rate is not carried across: it stays on the ICore side, and a block
configured with an explicit positive rate reports that the rate did not
cross.
Notes
- Algebraic, with no state – pure signal reindexing; nothing is scaled.
- Deliberately carries no state space. It re-indexes, and a D matrix can rescale a signal but never re-index one; the result is not linear in the pair (u, P) either. Model reduction is right to report the block as unmergeable.
- Permute Dimensions is a different block: it reorders the two DIMENSIONS from a config vector, which on a 2-D signal means the transpose. This one reorders within a dimension, from a port, and can change the signal's length.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Matrix_Operations/Permute_Matrix |
| family | Control_Systems/Matrix_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Permute_Matrix |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Permute_Matrix/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Permute_Matrix.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Permute_Matrix/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Permute_Matrix.h |
| default size on canvas | 100 × 80 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | in | ICoreDouble | P |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Permute | Rows%~%Columns~~Columns | mode |
Index Base | One-based%~%Zero-based~~One-based | ZeroOneIdxMode |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Matrix Operations/Permute Matrix |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | errmode = Clip index, checkDims = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Permute | mode | passes through |
Index Base | ZeroOneIdxMode | passes through |
Caveat (shown to the user): the axis and the index base cross one for one; ICore always CLIPS an out-of-range index, which is Simulink's default, so errmode is pinned rather than offered and a model set to "Clip and warn" or "Generate error" is reported on import instead of silently changing meaning. P's length -- not the input's size -- sets the permuted dimension on both sides, so checkDims is pinned off to match
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Permute Matrix -- the input's rows or columns re-emitted in the order a PORT names Measured against Simulink R2026a on [1 2 3; 4 5 6]:
Columns, P = [3 1 2] -> [3 1 2; 6 4 5] Rows, P = [2 1 2] -> a 3x3 - repeats are allowed, and the output is TALLER than the input, so its size follows P's LENGTH rather than the input's P = [1.7 2.2 3.9] -> columns 1, 2, 3: the index is FLOORED P = [-2 0 2], one-based -> columns 1, 1, 2: out of range is CLIPPED into [1, N] Zero-based, P = [2 0 1] -> the same as one-based [3 1 2]
So the runtime rule everywhere is: floor(P), add one if the base is zero, clamp into [1, N]. ICore always clips -- Simulink's default -- and its two other errmode settings are pinned off by the catalog entry rather than offered, so a model carrying one is reported on import instead of silently changing meaning.
HDL is SYNTHESIZABLE, and the runtime index is what makes it interesting: fx_to_int is an arithmetic shift right, i.e. exactly the floor() the software targets use, and the clamped result then indexes the input array directly. See the header for the one caveat that follows from P arriving quantized.
Algebraic and stateless. No state space -- see the header for why.
Sample results#
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|---|
| 0 | -2 | -2 | -2 |
| 0.4 | 0.5 | 0.5 | 0.5 |
| 0.8 | -2 | -2 | -2 |
| 1.2 | 0.5 | 0.5 | 0.5 |
| 1.6 | -2 | -2 | -2 |
| 2 | 0.5 | 0.5 | 0.5 |
| 2.4 | -2 | -2 | -2 |
| 2.8 | 0.5 | 0.5 | 0.5 |
| 3.2 | -2 | -2 | -2 |
| 3.6 | 0.5 | 0.5 | 0.5 |
| 4 | -2 | -2 | -2 |
| 4.4 | 0.5 | 0.5 | 0.5 |
| 4.8 | -2 | -2 | -2 |
| 5.2 | 0.5 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Matrix_Operations__Permute_Matrix.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).