Identity Matrix — Control Systems/Matrix Operations
Control_Systems/Matrix_Operations/Identity_Matrix · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Identity Matrix
Control Systems / Matrix Operations
Emits the identity: y = eye(r, c), with y(k,k) = 1 and every other entry 0.
Its size comes from a parameter or from an input signal, by Output Size Source. At the default it is a source with no input at all; set to inherit, it grows one input port and copies that signal's dimensions.
Ports
- ref – present only for Inherit from input port: a signal whose DIMENSIONS the output copies. Only its shape is used – the values on this port are never read, in the simulator or in any generated core, and the output is still an identity rather than anything derived from the input. Add or remove this port to match the chosen source; a mismatch is reported rather than guessed at.
- Output – y, the identity at the chosen size.
Parameters
- Output Size Source – where the size comes from. This changes the
block's PORTS, not just its arithmetic.
- Dimensions – from Output Dimensions below; no input port. The default, as in Simulink.
- Inherit from input port – from the signal on the ref port, which this option adds. Output Dimensions is ignored in this mode, exactly as Simulink ignores it there.
- Output Dimensions – the output's size under Dimensions.
Either a single number
n, meaning the square [n,n], or a pair[r,c], meaning a rectangular identity with ones as far as the shorter side reaches. Defaults to5, as in Simulink. Note this differs from Expand Scalar, where a single number is a column length: each block follows its own Simulink counterpart rather than a shared convention. - Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. The value emitted never changes, so the rate only decides how often the port is refreshed.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Nothing is exposed as a tunable parameter – an identity has no free values, so unlike Constant and Expand Scalar this source puts nothing on the params object – and the size is structural, fixed into every signal declaration at export time. Each target writes the ones and the zeros out entry by entry rather than calling its own eye helper. Like Constant this source reads no clock, so the three HDL targets are genuinely synthesizable: two Q16.16 literals driven onto the signal, with no arithmetic at all.
Simulink bridge
Import and export, mapped to
simulink/Matrix Operations/IdentityMatrix (the Simulink block's name has
no space in it). "Output Dimensions" goes to OutputDimensions as a
pass-through value, "Output Size Source" to
InheritOutputPortAttributes (Dimensions →
off, Inherit from input port → on), one
option for one option so that round trip is lossless, and "Sampling Time (s)" to
SampleTime as on every block.
The port count is not a parameter on either side: Simulink grows its own
input port when InheritOutputPortAttributes is set, so export writes
nothing extra, and import reads that value to widen the ICore port list to match.
This is the only block in the library that goes from zero ports to one
that way – every other port-moving parameter widens a block that already
had an input.
Simulink's OutDataTypeStr is its fixed-point tooling and has no
ICore counterpart – every ICore signal is a double – so it is left at
its default.
Notes
- Algebraic and stateless, and time-independent: the output is the same at every instant, in both modes – a port's SIZE is fixed for a run, so an inherited identity never changes either.
- No state space, in either mode. Under Dimensions there is no input for a D·u to act on, exactly as with Constant; under Inherit from input port there is an input, but its values are never read, so the output is not a function of it at all and no D represents the block.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Matrix_Operations/Identity_Matrix |
| family | Control_Systems/Matrix_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Identity_Matrix |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Identity_Matrix/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Identity_Matrix.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Identity_Matrix/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Identity_Matrix.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Output Size Source | Dimensions%~%Inherit from input port~~Dimensions | InheritOutputPortAttributes |
Output Dimensions | 5 | OutputDimensions |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Matrix Operations/IdentityMatrix |
| port-count rule | PortsParam::IdentityInheritAttributes |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Output Dimensions | OutputDimensions | passes through |
Output Size Source | InheritOutputPortAttributes | Dimensions → off, Inherit from input port → on |
Caveat (shown to the user): OutDataTypeStr is Simulink's fixed-point tooling and has no ICore counterpart -- every ICore signal is a double -- so it is left at its default. Under "Inherit from input port" both sides IGNORE OutputDimensions and take the shape from the input signal, whose values neither side reads.
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 2 entries for 1 port (0 in, 1 out) — grouped, or one undocumented? a reader must say
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Identity Matrix block -- y = eye(r, c) A SOURCE emitting ones on the main diagonal and zeros everywhere else. "Output Dimensions" takes the same two forms Simulink's does, and their meanings were read off the real block rather than assumed: a single number 4 compiles to a 4x4, and a pair [3 2] to a 3x2 with ones at (0,0) and (1,1). Note the single number means the SQUARE matrix here, where Expand Scalar's means a column length -- the two blocks genuinely differ, and each follows its own Simulink counterpart.
THE BLOCK IS A SOURCE, OR NOT, BY "Output Size Source". At its default it takes no input and sizes itself from the parameter. Set to inherit, it grows ONE input port and copies that signal's DIMENSIONS -- Simulink's InheritOutputPortAttributes = 'on', which the bridge carries as PortsParam::IdentityInheritAttributes.
THE INHERITED PORT CARRIES ONLY A SHAPE. Its values are never read, in the simulator or in any generated core, and the output is still eye() rather than anything derived from the input. That was confirmed against the real Simulink block rather than assumed, because "inherit attributes" could plausibly have meant a pass-through: fed a 2x3 of 7..12 it returns [1 0 0; 0 1 0], and fed a 3x3 of 1..9 it returns eye(3). Its OutputDimensions is IGNORED in that mode too -- setting [5 5] against a 2x3 input still gave a 2x3 -- which is why this block reads the port instead of reconciling the two.
IT IS THE ONLY BLOCK IN THE LIBRARY THAT GOES FROM ZERO PORTS TO ONE. Every other port-moving parameter widens a block that already had an input, which is why the recipe codec's port-edit guard had to admit a zero default -- see PortsParam::IdentityInheritAttributes.
NOTHING IS TUNABLE: an identity has no free values. The size is structural, fixed into every signal declaration at export time.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Matrix_Operations__Identity_Matrix.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).