Extract Diagonal — Control Systems/Matrix Operations
Control_Systems/Matrix_Operations/Extract_Diagonal · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Extract Diagonal
Control Systems / Matrix Operations
Collects the main diagonal of a matrix into a column:
y(k) = u(k,k), which is MATLAB's diag applied to a matrix.
A non-square input is not an error: the diagonal simply stops at the shorter side, so an [m,n] input gives min(m,n) entries. Simulink's own block does the same, and a 3×2 there returns the two entries u(1,1) and u(2,2).
Ports
- u – the matrix to read, of any size [m,n]. Only the entries u(k,k) are read; everything off the diagonal is ignored.
- Output – y, a column of min(m,n) entries carrying the diagonal top-left to bottom-right.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Nothing is exposed as a tunable parameter: which entries are read is structural and is fixed into the generated code at export time, written out one assignment per diagonal entry rather than as a call to each language's own diagonal helper. The three HDL targets are fully synthesizable: selecting entries is a rewiring, so the cores carry plain assignments with no arithmetic.
Simulink bridge
Import and export, mapped to
simulink/Matrix Operations/Extract Diagonal. Nothing crosses but the
block itself: the Simulink block is a masked S-Function that defines
no dialog parameters at all, not even SampleTime, so the
entry sets hasSampleTimeParam = false and "Sampling Time (s)" stays
on the ICore side. Writing that parameter anyway would be a hard
set_param error in MATLAB rather than a warning, aborting the whole
generated script.
Notes
- Algebraic, with no state: the output depends only on the current input.
- To go the other way – a vector into a diagonal matrix –
use Create Diagonal Matrix. MATLAB's
diagchooses between the two meanings by looking at its argument's shape; Simulink splits them into two blocks, and so does ICore. In particular this block handed an [n,1] column returns the single entry u(1,1), because a column's diagonal is one element long – it does not build a matrix. - No state space, deliberately. Reading u(k,k) walks ACROSS the signal's columns, which no left multiplication y = D·u of the signal matrix can express, so model reduction reports the block as unmergeable rather than merging a matrix that does not represent it.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Matrix_Operations/Extract_Diagonal |
| family | Control_Systems/Matrix_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Extract_Diagonal |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Extract_Diagonal/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Extract_Diagonal.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Extract_Diagonal/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Extract_Diagonal.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Matrix Operations/Extract Diagonal |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the rate does not cross: Simulink's Extract Diagonal is a masked S-Function that defines no dialog parameters at all, so "Sampling Time (s)" stays on the ICore side
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Extract Diagonal block -- y = diag(u), the main diagonal as a column MATLAB's diag() applied to a MATRIX: the entries u(k,k) collected into a column. An [m,n] input gives a [min(m,n), 1] output.
THE NON-SQUARE CASE IS NOT AN ERROR, and that was confirmed against the real Simulink block rather than assumed, because rejecting it would have been the plausible reading: a 3x2 fed to Simulink's Extract Diagonal comes back as the 2-element [u(0,0), u(1,1)], stopping at the shorter side. min(m,n) is therefore the block's size rule, not a special case bolted on.
THE MIRROR OF Create Diagonal Matrix, which goes the other way. On a vector the two are not inverses in the shape a reader might expect: this block handed an [n,1] column reads its single diagonal entry u(0,0) and produces a scalar, because min(n,1) is 1 -- exactly what MATLAB's diag() of a column would NOT do (it builds a matrix). MATLAB reads the ARGUMENT's shape to choose between the two meanings; Simulink splits them into two blocks and so does ICore, which is why the description says which one a user wanting the other is looking for.
NO STATE SPACE, deliberately -- see the header.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -2 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | -2 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | -2 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | -2 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | -2 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | -2 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | -2 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Matrix_Operations__Extract_Diagonal.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).