Expand Scalar — Control Systems/Matrix Operations
Control_Systems/Matrix_Operations/Expand_Scalar · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Expand Scalar
Control Systems / Matrix Operations
A source that emits a matrix whose every entry is the same number:
y = v · ones(r, c)
It has no input port, and that is the block's one surprise: the scalar it expands is the Element Value parameter, not a signal. Simulink's own Expand Scalar is a source too. To widen a scalar SIGNAL into a matrix, use a Gain with a matrix gain in element-wise mode – a scalar signal against an [r,c] gain takes the gain's shape – or a Bias with a matrix bias.
Ports
- Output – y, of the size given by Output Dimensions, with the same Element Value in every entry.
Parameters
- Element Value – v, the number every entry carries. A scalar; its own shape is ignored, since the output's shape comes from the parameter below.
- Output Dimensions – the output's size. Either a single number
n, meaning an [n,1] column, or a pair[r,c]. Defaults to5, as in Simulink, which there is a 1-D signal of width five and here is a [5,1] column – an ICore signal is always two-dimensional, so a single number becomes a column exactly as it does in Reshape's Customize. - Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. The value emitted never changes, so the rate only decides how often the port is refreshed.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Element Value is exposed as a tunable parameter on the generated core, so a deployed core can be re-pointed at a different value without regenerating it; Output Dimensions is structural and is fixed into every signal declaration at export time, which is why it is not tunable. Like Constant, this source reads no clock, so the three HDL targets are genuinely synthesizable: one Q16.16 parameter driven onto every entry, with no real arithmetic anywhere.
Simulink bridge
Import and export, mapped to
simulink/Matrix Operations/Expand Scalar. "Element Value" goes to
ElementValue and "Output Dimensions" to
OutputDimensions, both as pass-through values, and "Sampling Time
(s)" to SampleTime as on every block. Simulink's
OutDataTypeStr is its fixed-point tooling and has no ICore
counterpart – every ICore signal is a double – so it is left at its
default.
Notes
- Algebraic and stateless, and time-independent: the output is the same at every instant, so nothing about it changes if the solver's rate or start time does.
- No state space: there is no input for a D·u to act on, exactly as with Constant.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Matrix_Operations/Expand_Scalar |
| family | Control_Systems/Matrix_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Expand_Scalar |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Expand_Scalar/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Expand_Scalar.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Expand_Scalar/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Expand_Scalar.h |
| default size on canvas | 75 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Element Value | 1 | ElementValue |
Output Dimensions | 5 | OutputDimensions |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Matrix Operations/Expand Scalar |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Element Value | ElementValue | passes through |
Output Dimensions | OutputDimensions | passes through |
Caveat (shown to the user): Simulink's OutDataTypeStr is its fixed-point tooling and has no ICore counterpart -- every ICore signal is a double -- so it is left at its default. An OutputDimensions of a single number n is a 1-D signal of width n in Simulink and an [n,1] column here, ICore having no 1-D signal.
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Expand Scalar block -- y = v * ones(r, c), one value in every entry A SOURCE, which is the block's one surprise and was confirmed against the real Simulink block rather than assumed: "Expand Scalar" sounds like it takes a scalar SIGNAL and widens it, but Simulink's has no input port at all -- its compiled inport list is empty -- and the scalar it expands is the ElementValue PARAMETER. So this block emits a matrix whose every entry is one configured number, and the description says so where a user reaching for a signal-widening block will read it (a Gain against a matrix K is that block).
THE SIZE IS THE PARAMETER'S, exactly as Reshape's Customize shape works: a single number n gives an [n,1] column, a pair [r,c] gives that. Simulink writes the same two forms -- an OutputDimensions of 5 compiles to a 1-D signal of width five, and [3 2] to a 3x2 -- and ICore has no 1-D signal, so the single number lands as a column.
THE VALUE IS TUNABLE ON THE GENERATED CORE and the SIZE is not: the size is structural, baked into every signal declaration at export time, while the value rides on the shared params object exactly as Constant's K does.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Matrix_Operations__Expand_Scalar.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).