Interval Test — Control Systems/Logic And Bit Operations
Control_Systems/Logic_And_Bit_Operations/Interval_Test · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Interval Test
Control Systems / Logic And Bit Operations
Answers 1 where an entry of the input lies inside a fixed interval and 0 where it does not: y = (u ≥ lo) ∧ (u ≤ up), with each end independently made open instead, so the test becomes strict at that end. The comparison is applied entry by entry, so a matrix signal is treated element for element and the signal's size is unchanged.
Ports
- Input – the signal u to be tested, of any size [m,n].
- Output – y, of the SAME size [m,n] as the input. Every entry is 1 or 0. It is carried as an ordinary real signal, not a boolean type – every port in this library is a real matrix – so it can be fed straight into arithmetic as a 0/1 mask.
Parameters
- Lower Limit – the scalar lo. Defaults to −0.5, as in Simulink. A per-entry limit sized like the input is not implemented and is reported rather than broadcast from its first entry.
- Upper Limit – the scalar up. Defaults to 0.5, as in Simulink, and must not be below the lower limit – an inverted pair makes the interval empty and is reported.
- Lower Bound – whether the lower limit itself counts as inside.
- Closed (u >= lower limit) – it does. The default, as in Simulink.
- Open (u > lower limit) – it does not.
- Upper Bound – the same choice at the other end.
- Closed (u <= upper limit) – the upper limit counts as inside. The default, as in Simulink.
- Open (u < upper limit) – it does not.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. All four choices are baked into the generated code
at export time rather than exposed as tunable parameters: the limits as
literals, the two bound kinds as the comparison operators themselves. The three
HDL targets are fully synthesizable – two signed compares and a
conjunction, with no arithmetic – so nothing is evaluated in
real.
Simulink bridge
Import and export, mapped to simulink/Logic and Bit Operations/Interval
Test. "Lower Limit" to lowlimit and "Upper Limit" to
uplimit as plain pass-through values; "Lower Bound" to
IntervalClosedLeft and "Upper Bound" to
IntervalClosedRight, each with its two options mapped onto
on and off, so all four round trip losslessly.
OutDataTypeStr is always written as boolean: this
block has no data-type choice to offer, and pinning it is what keeps the two
sides comparing the same thing.
The Simulink block defines no SampleTime parameter, so
"Sampling Time (s)" does not cross – a block left at the inheriting
default loses nothing, and one given an explicit period is reported rather than
silently dropped. It defines no ZeroCross either, unlike the two
Compare blocks.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear – the output is a two-valued step function of the input – so the block deliberately carries no state space and model reduction reports it as unmergeable.
- The two ends are independent: closed on one and open on the other is the half-open interval that tiles without overlap, which is what makes a stack of these blocks a clean partition.
- An HDL core sees its input already quantized to one part in 1.5×10⁻⁵, and rounds both limits to the nearest value on the same lattice, so an entry within one quantum of either limit can land on the other side of it. The open/closed distinction is exactly one quantum wide there – on the HDL targets it is only meaningful for a limit that is exactly representable in Q16.16.
- For limits that arrive on ports rather than from config, use Interval Test Dynamic.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Logic_And_Bit_Operations/Interval_Test |
| family | Control_Systems/Logic_And_Bit_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Interval_Test |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Logic_And_Bit_Operations/Interval_Test/ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Interval_Test.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Logic_And_Bit_Operations/Interval_Test/ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Interval_Test.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Lower Limit | -0.5 | lowlimit |
Upper Limit | 0.5 | uplimit |
Lower Bound | Closed (u >= lower limit)%~%Open (u > lower limit)~~Close… | IntervalClosedLeft |
Upper Bound | Closed (u <= upper limit)%~%Open (u < upper limit)~~Close… | IntervalClosedRight |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Logic and Bit Operations/Interval Test |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | OutDataTypeStr = boolean |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Lower Limit | lowlimit | passes through |
Upper Limit | uplimit | passes through |
Lower Bound | IntervalClosedLeft | Closed (u >= lower limit) → on, Open (u > lower limit) → off |
Upper Bound | IntervalClosedRight | Closed (u <= upper limit) → on, Open (u < upper limit) → off |
Caveat (shown to the user): all four parameters map 1:1 onto the Simulink block's, so the choice is lossless in both directions; the Simulink block has NO SampleTime parameter, so "Sampling Time (s)" does not cross
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Interval Test block -- is each entry inside a fixed interval? y = 1 where lo <(=) u <(=) up holds and y = 0 where it does not, with each END independently CLOSED (the limit itself counts as inside) or OPEN. Applied INDEPENDENTLY to every entry of the input signal, so the output keeps the input's size.
Measured against R2026a rather than assumed (u swept over {-1, -0.5, 0, 0.5, 1, 2} at lo = -0.5, up = 0.5):
closed/closed 0 1 1 1 0 0 closed/open 0 1 1 0 0 0 open/closed 0 0 1 1 0 0 open/open 0 0 1 0 0 0
i.e. "closed left" is u >= lo and "closed right" is u <= up, each end on its own.
The output is a REAL signal carrying 1.0 and 0.0, not a boolean type -- every port in this library is ICoreDouble. Simulink's counterpart emits a
boolean, which logs as 1/0, so the two agree numerically; the bridge pins OutDataTypeStr to boolean so that stays true.Code export: all four choices are STRUCTURAL. The two limits are inlined as export-time literals and the two closed/open flags are emitted as the comparison operators themselves, so a generated core carries one test rather than a switch over four.
HDL: fully synthesizable. Two signed compares and an AND, no arithmetic, so the three HDL cores stay in the fixed-point datapath. The datapath's usual caveats apply at the boundaries -- see the block's description.
Algebraic and stateless. No state space -- see the header.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.