Float Extract Bits — Control Systems/Logic And Bit Operations

Float Extract Bits

Control Systems / Logic And Bit Operations

Reads its input as an IEEE-754 floating-point number and answers a contiguous field of the bits that represent it: y = (bits(u) ÷ 2^low) mod 2ⁿ, with bit 0 the LEAST significant bit. The word is one sign bit at the top, then E biased exponent bits, then M mantissa bits – 1/8/23 for a single, 1/11/52 for a double. Applied entry by entry, so a matrix signal keeps its size.

Ports

• Input – the number u, of any size [m,n]. It is first ROUNDED to the chosen float type, exactly as feeding Simulink's block through a Data Type Conversion does, and the bits of that rounded value are what is read.
• Output – y, of the SAME size [m,n], carrying the requested field as an ordinary real signal.

Parameters

• Output Mode – which field is taken. This selects the field rather than retuning it, so each option is its own code path.
  • All bits – the whole word: low = 0, n = W. The default, as in Simulink. On a double this is a 64-bit field and is refused – see Notes.
  • Range of bits – the window named by Bit Range.
  • Sign – the top bit alone: 1 for a negative value, 0 otherwise. A negative zero reports 1, as IEEE-754 says and as Simulink answers.
  • Mantissa – the low M bits, with no implied leading one.
  • Exponent – the E BIASED exponent bits: 127 for 1.0 as a single, 1023 as a double. Zero and the subnormals report 0; an infinity or a NaN reports all ones.
• Bit Range – a two-entry [low high] pair, INCLUSIVE at both ends, used only in Range of bits. The low bound must not exceed the high one – Simulink makes that a hard error and so does this block. A window reaching above the top of the word reads zeros there.
• Input Float Type – single (8 exponent, 23 mantissa) or double (11 exponent, 52 mantissa): which layout the bits are read in, and which type the input is rounded to first. This has no Simulink parameter behind it – see Simulink bridge.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text – but not every one of them in every configuration, and a target that cannot carry the configuration refuses it by name rather than exporting arithmetic that overflows in silence.

• The three HDL targets carry this library's arithmetic in Q16.16 fixed point, so the value reaching the generated body has already been quantized and has no IEEE-754 mantissa left to read – bits below 2⁻¹⁶ are gone. What survives quantization is the MAGNITUDE, which is what the sign and the exponent are made of. So those three implement any field lying entirely at or above bit M – Sign, Exponent, and a Range of bits that does not reach into the mantissa – and refuse the rest. They also refuse a field wider than 15 bits, because the answer goes back out through a Q16.16 port that tops out at 32767.
• PLC Structured Text has a real LREAL and keeps every field the software targets do, up to the 2147483647 its TRUNC yields as a DINT. So it refuses All bits and a double's Mantissa, and carries the rest.
• The seven software targets carry every configuration the block accepts at all.

The field, the layout and every power of two are resolved when the model is built and inlined as literals; nothing here is a tunable parameter on the generated core.

Simulink bridge

Import and export, mapped to simulink/Logic and Bit Operations/Float Extract Bits. Output Mode → OutputMode and Bit Range → BitRange, both 1:1 and lossless: the enum table is Simulink's own five strings.

"Input Float Type" does NOT cross, and is reported rather than dropped. In Simulink the layout comes from the input SIGNAL's data type, which is a property of the wire and not a parameter of the block, so there is no set_param that could carry it – a model crossing either way needs a Data Type Conversion of the matching type in front of the block. This is the same gap Extract Bits carries for its word length, and for the same reason: every ICore wire is a matrix of doubles.

The rate does NOT cross. That block defines no SampleTime parameter – verified by set_param against R2026a, which answers "FloatExtractBits block does not have a parameter named 'SampleTime'" – so "Sampling Time (s)" stays on the ICore side.

Notes

• Algebraic and stateless. Deliberately carries no state space: reading a bit field is a piecewise-constant function of the input, so there is no A/B/C/D that represents it.
• A field wider than 53 bits is refused by the block itself, in every language and in the live run, because an ICore signal carries whole numbers exactly only that far. That is exactly All bits on a double, whose word is 64 bits wide. On a single the whole 32-bit word fits exactly and All bits is offered.
• Negative zero is the one place the HDL targets cannot agree with the others. IEEE gives −0 a sign bit of 1 and Simulink reports it; Q16.16 fixed point has no negative zero at all, so an HDL core reports 0 there. Every other input agrees exactly. This is the port's limit rather than the block's, and it is stated here because nothing else would reveal it.
• An HDL core reads the exponent of the QUANTIZED value. Where the input is exactly representable in Q16.16 – any multiple of 2⁻¹⁶ below 32768 – that is the same number the other targets read. Where it is not, the two can differ by one for a sample lying within a quantum of a power of two.
• An infinity reports an exponent of all ones and a mantissa of zero; a NaN reports all ones and a quiet-NaN mantissa. A NaN's own payload does not survive.