Detect Rise Positive — Control Systems/Logic And Bit Operations

Detect Rise Positive

Control Systems / Logic And Bit Operations

Reports, as a 1.0/0.0 flag, whether u > 0 now and u > 0 was false on the previous sample:

y[k] = 1 on the sample where u first becomes strictly positive

Applied entry by entry, so a matrix signal is tested element for element and each entry remembers its own past independently.

Ports

• Input – the signal u being watched, of any size [m,n].
• Output – the flag y, of the same size as the input: 1.0 on a sample that satisfies the test and 0.0 on one that does not. The block never reshapes a signal.

Parameters

• Initial Condition (Previous Test Result) – seeds the one sample of memory: the value the block's own test is taken to have had on the sample before the run started, for every entry. It is a boolean seed – zero means the test started out false, and any nonzero value means it started out true, which is what Simulink does when it quantizes vinit to the delay's run-time type. Defaults to 0, so a signal that is already positive at t = 0 reports an edge on the first sample.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The initial condition is baked in as the state seed rather than exposed as a tunable parameter, since it only affects the first sample of a run.

On the three HDL targets the sign test is exact: zero is exactly representable in Q16.16, so the threshold this block compares against carries no quantization error at all, and the stored flag is exactly to_fx(1.0) or to_fx(0.0).

Simulink bridge

Import and export, mapped to simulink/Logic and Bit Operations/Detect Rise Positive. "Initial Condition (Previous Test Result)" to vinit. The Simulink counterpart has no SampleTime parameter – it is a masked subsystem that inherits the rate of whatever drives it – so "Sampling Time (s)" does not cross, and a block configured with an explicit positive rate reports that it did not carry over.

Simulink's InputProcessing is always implied as Elements as channels (sample based): an ICore signal has no frame dimension, so treating columns as channels has nothing to mean here, and pinning it is what stops an imported frame-based block from being silently read as a sample-based one.

Notes

• Stateful and discrete only: one sample of memory per entry, holding the previous value of the block's own test.
• Not linear, and so deliberately carries no state space – model reduction reports it as unmergeable rather than absorbing a comparison.
• An EDGE, not a level: a signal that stays positive reports 1 once and 0 thereafter. Detect Rise Nonnegative is the same edge with zero counted as part of the risen state.