Bitwise Operator — Control Systems/Logic And Bit Operations

Bitwise Operator

Control Systems / Logic and Bit Operations

Combines integer signals bit by bit: AND, OR, NAND, NOR and XOR over as many inputs as you give it, or NOT over one. The work is done entry by entry, so two [2,3] signals produce a [2,3] answer.

Ports

• Inputs (u32 by default) – two by default, and the count is user-editable. Every input carries the integer type chosen below and nothing else, because a bit operation is defined on a width. They must all be the same size [m,n], or be scalars, which are then combined with every entry of the others. NOT takes exactly one input; the other five take at least two.
• Output (u32 by default) – the result, of the inputs' shared size [m,n], carrying the same integer type.

Feeding it another type

Every port on this block carries one integer type, so a floating-point or differently-sized signal reaches it through a Data Type Conversion block – which puts the change of width on the canvas where you can see it. That is also Simulink's rule: its Bitwise Operator requires its inputs to share one integer type and gives that type back.

Parameters

• Operator – which combination is taken. This selects the operation rather than retuning it, so each option is a separate code path.
  • AND – a bit is set where it is set in every input. The default, as in Simulink.
  • OR – set where it is set in any input.
  • NAND – the negation of AND.
  • NOR – the negation of OR.
  • XOR – set where an ODD number of inputs has it set, which is what chaining exclusive-or across several inputs means.
  • NOT – every bit of a single input flipped.
• Operate on data type – the integer type every port carries, and therefore the width the result is taken to. The list is every integer type the application knows, so it grows when the application does. Defaults to a 32-bit unsigned integer.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

What the width does to the answer

The result is taken to the chosen width when it is stored, which is where NOT becomes interesting: on an 8-bit unsigned output, NOT of 5 is 250, and on an 8-bit signed output the same operation gives −6. Those are the same bits read two ways, and choosing the type is choosing which reading you get. Nothing is clamped: a result that does not fit wraps around, which is what a fixed-width integer does everywhere.

Code export

Python, MATLAB, Java, Rust, C, C++ and PLC Structured Text carry this block. The operator and the width are fixed into the generated code at export time.

VHDL, Verilog and SystemVerilog are not applicable for this block at any setting, and are refused by name at export time with the reason rather than producing a number that would differ from the simulation. Those three targets carry every signal in one fixed-point format and do not yet apply a signal's type to it, and every port on this block is an integer. The refusal is recorded as "not applicable", never as a failure.

Simulink bridge

Import and export, mapped to simulink/Logic and Bit Operations/Bitwise Operator. "Operator" to logicop, one option for one option (AND, OR, NAND, NOR, XOR, NOT), so that round trip is lossless; the input port count becomes Simulink's NumInputPorts number and an imported count becomes this port list.

UseBitMask is always written as off: Simulink's block can instead combine ONE input against a stored mask, which here is a Constant wired into a second port – visible on the canvas, and one fewer parameter to keep in step. Operate on data type does not cross, because Simulink's block has no data-type parameter at all – it takes the type from the signal reaching it, which is the same type this block's ports carry, so the two agree without a parameter. Simulink's block has no sampling-time parameter, so a rate set here stays on this side and is reported rather than silently dropped.

Notes

• Algebraic, with no state: the output depends only on the current inputs.
• Not linear, so the block deliberately carries no state space and model reduction reports it as unmergeable.
• A 64-bit integer type is exact only to about 9 007 199 254 740 992 (2⁵³): values are carried as 64-bit floats during a run, and a 64-bit float cannot hold every 64-bit integer. The narrower types are exact.