LTV System — Control Systems/Linear Parameter Varying
Control_Systems/Linear_Parameter_Varying/LTV_System · 1 input / 3 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
LTV System
Control Systems / Linear Parameter Varying
Simulates a linear time-varying state-space model given at the breakpoints of a time grid: a set of matrices A, B, C and D for each grid time, interpolated between them, with operating-point offsets:
y = C(t)·(x − x0) + D(t)·(u − u0) + y0
dx = A(t)·(x − x0) + B(t)·(u − u0) + dx0
For a discrete model the next state is dx, and the grid counts
samples: a breakpoint of 50 is the 50th sample, as in an
ltvss with a discrete time grid. For a continuous model the
grid is in seconds and the state is integrated by forward Euler at the
block's sampling time.
It is Control System Toolbox's LTV System block, with the model array
given as stacked matrices instead of an ss array.
Ports
- u – the input, a column [m,1].
- y – the output, a column [p,1].
- x – the state at this sample, [n,1].
- dx – the next state (discrete) or the state derivative (continuous), [n,1].
Parameters
- Time Grid – the K strictly increasing grid times (samples for a discrete model, seconds for a continuous one), at least two.
- Model Type – Discrete or Continuous.
- A – the K state matrices stacked vertically, [n·K, n], in grid order. n is 1 to 8.
- B – the K input matrices stacked, [n·K, m].
- C – the K output matrices stacked, [p·K, n].
- D – the K feedthrough matrices stacked, [p·K, m]. The four tables together may hold at most 4096 numbers.
- Initial State – x at the first sample, [n,1].
- Input Offset u0, Output Offset y0, State Offset x0, Derivative Offset dx0 – the operating point, [m,1], [p,1], [n,1], [n,1]; a scalar is repeated.
- Offsets Are Equilibrium – On (Simulink's default) treats the offsets as an equilibrium and ignores dx0: dx0 is taken as x0 for a discrete model and as 0 for a continuous one. Off uses dx0 as given.
- Interpolation – Flat (the breakpoint at or below), Nearest (ties go up) or Linear.
- Extrapolation – Clip holds the end matrices; Linear extends the end segments, and needs Linear interpolation.
- Sampling Time (s) – the block's rate; a continuous model is stepped by forward Euler at it.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each prints the same description of the step that the simulation itself runs – the grid search, the interpolation and the state update – so every target does the same arithmetic in the same order. The tables are baked in as constants.
⚠ The three HDL targets run in simulation-only real arithmetic, quantizing only at the port boundaries.
Simulink bridge
None (Support::None). Simulink's block takes its model as
one ss array with a sampling grid, evaluated from a MATLAB expression,
which the bridge cannot build from this block's stacked matrices or read back into
them; the bridge reports this block rather than dropping it silently. Code export
verification still covers it across all ten languages.
Notes
- Discrete only, and stateful: the state and a sample counter persist; the grid is read against the counter, so the model starts at the grid's time 0 on the first sample.
- Simulink's state-space bus and offset bus outputs and its delays are not offered.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Linear_Parameter_Varying/LTV_System |
| family | Control_Systems/Linear_Parameter_Varying |
| solver environment class | ICoreBlock_0_Control_Systems_1_Linear_Parameter_Varying_2_LTV_System |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Linear_Parameter_Varying/LTV_System/ICoreBlock_0_Control_Systems_1_Linear_Parameter_Varying_2_LTV_System.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Linear_Parameter_Varying/LTV_System/ICoreBlock_0_Control_Systems_1_Linear_Parameter_Varying_2_LTV_System.h |
| default size on canvas | 140 × 90 px |
| ports at insert | 1 in, 3 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | y |
| 3 | out | ICoreDouble | x |
| 4 | out | ICoreDouble | dx |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Time Grid | [0 50 100] | — |
Model Type | Discrete%~%Continuous~~Discrete | — |
A | [0.9 0.1; -0.1 0.8; 0.7 0.2; -0.2 0.85; 0.95 0; 0.1 0.6] | — |
B | [1; 0.5; 0.8; 0.3; 1.2; 0.4] | — |
C | [1 0; 0.9 0.2; 1.1 -0.1] | — |
D | [0; 0; 0] | — |
Initial State | [0; 0] | — |
Input Offset u0 | 0 | — |
Output Offset y0 | 0 | — |
State Offset x0 | 0 | — |
Derivative Offset dx0 | 0 | — |
Offsets Are Equilibrium | On%~%Off~~On | — |
Interpolation | Flat%~%Nearest%~%Linear~~Linear | — |
Extrapolation | Clip%~%Linear~~Clip | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): Simulink's LTV System takes its model as one ss array with a sampling grid, evaluated from a MATLAB expression, which the bridge cannot build from stacked matrices or read back into them. The block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
LTV System -- a state-space model gridded over time, Control System Toolbox's LTV System A(t), B(t), C(t), D(t) at the breakpoints of a time grid, interpolated between them (Flat, Nearest or Linear; Clip or Linear extrapolation), with operating-point offsets:
y = C(t) (x - x0) + D(t) (u - u0) + y0 dx = A(t) (x - x0) + B(t) (u - u0) + (equilibrium ? (discrete ? x0 : 0) : dx0)
A DISCRETE model's grid counts SAMPLES (x[k+1] = dx at sample k); a CONTINUOUS one's counts seconds, t = k*Ts, and its state steps by forward Euler at the block's rate. The arithmetic is ICoreGriddedStateSpaceSupport's, shared with LPV System.
⚠ MEASURED AGAINST R2026a's LTV System (discrete and continuous under ode1, both offset conventions): at most 1.8e-15, the continuous-equilibrium case bit for bit on all 60 samples; and the emitted Python is bit-identical to the live run (800 / 800 samples over the LTV and LPV probes).
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.