Discrete Varying Notch — Control Systems/Linear Parameter Varying

Discrete Varying Notch

Control Systems / Linear Parameter Varying

A second-order notch filter whose centre frequency, depth and damping all arrive on ports, so it may be re-tuned on every sample:

N(s) = (s² + 2·g_min·ζ·w₀·s + w₀²) / (s² + 2·ζ·w₀·s + w₀²)

discretized by the bilinear (Tustin) rule and realized as a biquad in transposed direct form II (two states).

Ports

• u – the signal to filter, of any size [p,q]. The filter is SISO and applied independently to every entry, each carrying its own pair of states, but all entries share the one parameter triple.
• frequency – the notch centre w₀ in radians per second, scalar.
• gmin – the notch depth: the gain at the centre frequency. 0 is an infinitely deep notch, 1 removes the notch entirely (numerator and denominator become equal), and values between set the attenuation.
• damping – the damping ratio ζ, which sets how WIDE the notch is: larger is wider.
• Output – y, the same size as u.

Parameters

• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is also the T_s the Tustin coefficients are formed from, so it changes the filter and not merely how often it runs.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. All three parameters are read from their ports each step and the biquad is formed there, so a generated core re-tunes exactly as the simulation does; only T_s is baked in.

The three HDL targets are SIMULATION-ONLY. Forming the coefficients divides by A₀ on every sample, which does not belong in a Q16.16 datapath, so those cores carry the filter in real arithmetic and quantize only at the port boundary – the same choice the sibling Discrete Varying Lowpass, Recursive IIR and Variable Transport Delay make.

Simulink bridge

Import and export, mapped to cstblocks/Linear Parameter Varying/Discrete Varying Notch (the library is cstblocks, not the "Control System Toolbox" display name, which add_block does not accept). The three parameters need no mapping – on both sides they are signals – and the port order (u, frequency, gmin, damping) is identical.

Simulink's w0 parameter is always written out as 0: on the varying block the centre frequency comes from the port, so leaving it free would let an imported block carry a second, silently unused frequency.

"Sampling Time (s)" DOES cross, under Simulink's own name for it here: this block's rate parameter is Ts, not SampleTime.

Notes

• Discrete only, and stateful: two states per entry, both starting at zero.
• The discretization and the realization are both part of the specification. Tustin as a transposed direct form II biquad matches Simulink to 6·10⁻¹⁵ with all three parameters moving; the identical Tustin biquad written as a direct y-recursion is out by ~0.33. The two agree exactly whenever the parameters hold still, so a fixed-parameter check cannot tell them apart.