Decrement To Zero — Control Systems/Increment Decrement
Control_Systems/Increment_Decrement/Decrement_To_Zero · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Decrement To Zero
Control Systems / Increment Decrement
Subtracts one from the signal but never lets it go below zero: y = max(u − 1, 0), applied entry by entry. It is the countdown that stops at zero rather than running negative – a loop counter, a retry budget, a debounce.
Ports
- Input – the signal u, of any size [m,n].
- Output – y, of the SAME size [m,n]. The block never reshapes a signal.
Parameters
- None. The step of one and the floor of zero are both the block itself, not settings. For a decrement that runs past zero use Decrement Real World; for any other floor use Saturation.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The step is inlined as a constant at export time rather than exposed as a tunable parameter – there is no parameter behind it to tune. The three HDL targets carry the arithmetic in Q16.16 fixed point and are fully synthesizable: a subtraction and a comparison against zero, with no shift and no function call.
Simulink bridge
Import and export, mapped to simulink/Additional Math & Discrete/Additional Math: Increment - Decrement/Decrement To Zero. There are no parameters to map in either direction: Simulink's counterpart is a masked subsystem whose dialog and mask parameter lists are both empty.
The rate does NOT cross. That same block defines no
SampleTime parameter, so "Sampling Time (s)" stays on the ICore
side; writing it anyway would be a hard set_param error that aborts
the generated script rather than a warning.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Nonlinear, so the block deliberately carries no state space – the clamp is a branch, and model reduction reports the block as unmergeable rather than absorbing a relation it cannot represent.
- A negative input comes out as zero, not as itself. The rule is a floor on the RESULT, so u = −3 answers 0 rather than −3 or −4. Measured against the Simulink block rather than inferred: "does not decrease below zero" is easy to read as "passes a negative through untouched", and it does not.
- The clamped branch is where this block differs from Decrement Real World; below u = 1 they part company entirely.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Increment_Decrement/Decrement_To_Zero |
| family | Control_Systems/Increment_Decrement |
| solver environment class | ICoreBlock_0_Control_Systems_1_Increment_Decrement_2_Decrement_To_Zero |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Increment_Decrement/Decrement_To_Zero/ICoreBlock_0_Control_Systems_1_Increment_Decrement_2_Decrement_To_Zero.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Increment_Decrement/Decrement_To_Zero/ICoreBlock_0_Control_Systems_1_Increment_Decrement_2_Decrement_To_Zero.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Additional Math & Discrete/Additional Math: Increment - Decrement/Decrement To Zero |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the rate does not cross: the Simulink block is a masked subsystem with no SampleTime parameter, so "Sampling Time (s)" stays on the ICore side
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Decrement To Zero block -- decrement with a floor at zero y = max(u - 1, 0), entry by entry, so the output keeps the input's size, where the step is one. Algebraic, stateless, and with no parameters at all.
MEASURED, NOT INFERRED. Driven with u = [2.5 -1.25 0.5 -0.005 0 100.75 -0.5 3 0.6 -3] at Ts = 0.01, the R2026a block answers a straight max(u - step, 0): every negative input comes out as ZERO rather than passing through, and 0.5 - 1 comes out as 0 rather than -0.5. The documented phrase "does not decrease the value below zero" reads equally well as "leaves a negative alone", and that reading is wrong.
NO state space: the clamp is a branch, not a matrix (see the header).
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | 0 |
| 0.4 | 0.5 | 0 |
| 0.8 | -2 | 0 |
| 1.2 | 0.5 | 0 |
| 1.6 | -2 | 0 |
| 2 | 0.5 | 0 |
| 2.4 | -2 | 0 |
| 2.8 | 0.5 | 0 |
| 3.2 | -2 | 0 |
| 3.6 | 0.5 | 0 |
| 4 | -2 | 0 |
| 4.4 | 0.5 | 0 |
| 4.8 | -2 | 0 |
| 5.2 | 0.5 | 0 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0 |
ramp | Ramp: slope 1 from t = 0 | 0 … 4.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 0 |
step | Step: 0 -> 1 at t = 1 s | 0 … 0 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Increment_Decrement__Decrement_To_Zero.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).