Controller 1D — Control Systems/Gain Scheduling
Control_Systems/Gain_Scheduling/Controller_1D · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
1D Controller
Control Systems / Gain Scheduling
The Aerospace Blockset's 1D Controller [A(v),B(v),C(v),D(v)]: a state-space controller whose four matrices are scheduled on one variable v. A matrix is stored for every breakpoint, and between two breakpoints the block blends them linearly.
dx/dt = A(v)·x + B(v)·y, u = D(v)·y + C(v)·x
M(v) = (1 − f)·Mk + f·Mk+1, where bpk ≤ v < bpk+1 and f = (v − bpk) / (bpk+1 − bpk). Outside the breakpoints the schedule clamps: below the first it uses the first matrix set, at or above the last it uses the last.
Ports
- y – the controller input (the measurement or the error), an [m,1] column, m being the column count of the B and D matrices.
- v – the scheduling variable, a scalar.
- u – the controller output, a [p,1] column, p being the row count of one C matrix.
Parameters
- A Matrices – the n×n A matrix for every breakpoint, stacked
vertically in breakpoint order: a [P·n, n] matrix. From a MATLAB array
A(:,:,k)the config isreshape(permute(A,[1 3 2]),[],size(A,2)). - B Matrices – the n×m B matrices, stacked the same way: [P·n, m].
- C Matrices – the p×n C matrices, stacked: [P·p, n].
- D Matrices – the p×m D matrices, stacked: [P·p, m]. All zero makes the controller strictly proper.
- Breakpoints – the P scheduling-variable values the matrices belong to, strictly increasing, at least two.
- Initial State – x at the start of the run: a scalar for every state, or an [n,1] column. Default 0.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
The defaults are a first-order example with two breakpoints; the Simulink block has no literal defaults (its dialog names workspace variables).
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The schedule is baked in as a chain of comparisons on v that assigns the interval and the fraction (the two clamped ends included), and a chain on the interval that assigns the blended matrices; the state integrates with forward Euler at the block's period, because the matrices move with v and there is no fixed system to discretize exactly. All ten are rendered from the one description of the arithmetic the block's own simulation runs.
The three HDL targets are simulation-only: the fraction divides by a signal
difference, so they compute in real arithmetic and quantize only at the ports.
VHDL keeps the arithmetic in a function of its own.
Simulink bridge
None (Support::None). The counterpart is aerolibschedule/1D
Controller [A(v),B(v),C(v),D(v)] in the Aerospace Blockset, and this block reproduces it
exactly – but its four matrix parameters are three-dimensional arrays, one slice
per breakpoint, and neither MATLAB's matrix literal syntax nor an ICore matrix config has a
three-dimensional form. So the schedule cannot cross in either direction; the block is
reported rather than exported without its matrices. It therefore has no parity testbench;
code export verification covers it.
Notes
- Stateful: n states. Direct feedthrough when some D matrix is nonzero, and also when the C matrices differ between breakpoints: u = C(v)·x then moves with v at the same instant.
- The breakpoint search is inclusive at the bottom of each interval: v exactly on an interior breakpoint starts the next interval, with fraction 0.
- Linear at any instant but scheduled, so it carries no state space and model reduction reports it as unmergeable.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Gain_Scheduling/Controller_1D |
| family | Control_Systems/Gain_Scheduling |
| solver environment class | ICoreBlock_0_Control_Systems_1_Gain_Scheduling_2_Controller_1D |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Gain_Scheduling/Controller_1D/ICoreBlock_0_Control_Systems_1_Gain_Scheduling_2_Controller_1D.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Gain_Scheduling/Controller_1D/ICoreBlock_0_Control_Systems_1_Gain_Scheduling_2_Controller_1D.h |
| default size on canvas | 150 × 90 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | y |
| 2 | in | ICoreDouble | v |
| 3 | out | ICoreDouble | u |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
A Matrices | [-1; -2] | — |
B Matrices | [1; 1] | — |
C Matrices | [1; 1] | — |
D Matrices | [0; 0] | — |
Breakpoints | [0 1] | — |
Initial State | 0 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): aerolibschedule/1D Controller [A(v),B(v),C(v),D(v)] computes exactly what this block does -- measured to 0 under ode1 -- but its four matrix parameters are THREE-DIMENSIONAL arrays, one slice per breakpoint, and neither MATLAB's matrix literal syntax nor an ICore matrix config has a three-dimensional form. So the schedule cannot cross in either direction, and an exported model would carry the ports and no controller. Reported rather than exported to a counterpart that would be missing its matrices
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
1D Controller [A(v),B(v),C(v),D(v)] -- a scheduled state-space controller dx/dt = A(v)*x + B(v)*y u = D(v)*y + C(v)*x x(0) = Initial State M(v) = (1 - f)*M[k] + f*M[k+1] on the breakpoint interval k that v falls in
MEASURED AGAINST R2026a. The masked subsystem is a Prelookup on the breakpoints ("Index and fraction", extrapolation CLIP, "use last breakpoint" off, binary search) feeding four copies of the Interpolate Matrix(x) arithmetic, an Integrator on A*x + B*y and an output Sum D*y + C*x. With n = 2 states, three breakpoints, x_initial [0.3; -0.2] and a scheduling variable sweeping PAST BOTH ENDS of the breakpoints, the real block under ode1 and a forward-Euler reference of exactly the program below agree to EXACTLY 0 over 600 samples. An extrapolating reading of the ends -- the fraction running on past 0 and 1 -- is out by 1.24, so the clamp is load-bearing.
Stepped runs and every export take the forward Euler step at the block's period: the matrices move with v, so there is no fixed system to discretize exactly.
Everything but the ports, the configs and the description is shared with the 2D and 3D Controllers, the Observer Form and the Self-Conditioned controller, in ICoreScheduledControllerBlockBase (../ICoreScheduledControllerSupport.h).
NO SIMULINK BRIDGE, for the Interpolate Matrix blocks' reason: the four matrix parameters are three-dimensional arrays (M(:,:,k) per breakpoint), and neither MATLAB's matrix literal syntax nor an ICore matrix config has that form -- so an exported model would carry the ports and no schedule. The configs here stack the matrices vertically instead, and the description gives the one line of MATLAB that produces them from the arrays.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0.09063 |
ramp | Ramp: slope 1 from t = 0 | 0 … 2.7 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.4643 … 0.3933 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -0.2895 … 0.56 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit 93133d604 · produced by docsSample --out <folder> --blocks Gain_Scheduled_Lead_Lag Controller_1D Controller_Blend_1D Controller_2D Controller_3D Observer_Form_1D Self_Conditioned_1D Line_Of_Sight_Access Orbit_Propagator_Kepler Attitude_Dynamics Attitude_Profile_Nadir_Pointing Attitude_Profile_Geographic_Pointing Multitaper_PSD Cross_Power_Spectral_Density Transfer_Function_Estimate Envelope_Spectrum Compose_String Scan_String --steps 60 · data docs/generated/samples/Control_Systems__Gain_Scheduling__Controller_1D.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).