Variable Integer Delay — Control Systems/Discrete

Variable Integer Delay

Control Systems / Discrete

Delays its input by a whole number of samples that can change while the run is in progress:

y[k] = u[k − d[k]]

The delay arrives on its own port as a count of samples, is rounded to the nearest whole number and clamped to Maximum Delay (samples). A delay of zero is direct feedthrough, and a delay reaching back past the start of the run reads the configured Initial Condition.

Ports

• u – the delayed signal, of any size [m,n]. This is what comes out delayed.
• d – the delay in samples, a scalar [1,1]. It applies to the whole signal, not per entry. Negative values are clamped to zero – nothing arrives before it was sent.
• Output – the delayed signal, the SAME size [m,n] as u.

Parameters

• Maximum Delay (samples) – the depth of the ring buffer, and so the longest delay the block can represent. Defaults to 100, as Simulink's upper limit does. A larger requested delay is clamped rather than growing the buffer, because a delay line that reallocates mid-run is a latency spike on a real target.
• Initial Condition – a scalar, what the block emits while the delay still reaches back past the start of the run. Defaults to 0. The whole buffer is pre-filled with it.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is the spacing of the line, so it is part of the arithmetic and not merely a schedule.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each carries the ring buffer as its state, pre-filled with the initial condition, and indexes it with the rounded delay exactly as the simulation does. Nothing about the delay is baked in – it is read from its port every tick.

The three HDL targets derive the read address in hardware with the generated fixed-point package's fx_to_int. Because the delay arrives already as a COUNT rather than as a time, there is no 1/dt scaling and so none of the half-sample rounding ambiguity the seconds-based delay blocks carry – this block is the one to reach for when an exact delay matters on hardware. A zero delay is special-cased to the input rather than read back from the buffer: the write is registered, so on that tick the addressed slot still holds its previous contents and reading it would return the value from a whole lap ago.

Simulink bridge

Import and export, mapped to simulink/Discrete/Variable Integer Delay. "Maximum Delay (samples)" to DelayLengthUpperLimit, "Initial Condition" to InitialCondition, and "Sampling Time (s)" to SampleTime as on every block. The Simulink block is the general Delay block configured to take its length from a port, so DelayLengthSource is always emitted as Input port and InitialConditionSource as Dialog – those are what make it this block rather than one of its siblings, and there is no choice to offer behind either.

It also imports Control System Toolbox's cstblocks/Linear Parameter Varying/Discrete Varying Delay, which computes exactly the same thing under different parameter names. That was measured against R2026a rather than assumed: its Td is in samples, rounded half-up, clamped to [0, TdMax], with u0 held until the buffer fills and a delay of zero passing straight through – term for term what this block does. The importer folds the path and translates TdMax → "Maximum Delay (samples)", u0 → "Initial Condition" and Ts → "Sampling Time (s)". Its TdFixed and PreventDirectFeedthrough have no counterpart here and are reported as unmapped: the first pins the delay to a constant, which a Constant on the delay port does instead, and the second forces a minimum of one sample, which this block cannot express. Export always emits the Discrete/Variable Integer Delay path, so a model imported from the Linear Parameter Varying palette comes back as its equivalent rather than as itself.

Notes

• Stateful: maximum delay + 1 past values of the signal port.
• Discrete by nature – the line advances one slot per sample.
• Compare with the seconds-based delays. Variable Time Delay and Entity Transport Delay take a transit time in seconds and divide by the sampling period; this block takes the count directly. Use this one when you are counting samples and that one when you are measuring time.
• Deliberately carries no state space. A pure delay is the transcendental factor e^(−sd), which no finite A/B/C/D expresses – and a time-varying one is not even time-invariant.