Transfer Fcn Lead Or Lag — Control Systems/Discrete

Transfer Fcn Lead or Lag

Control Systems / Discrete

A first-order compensator with both singularities given directly in the z plane:

H(z) = (z − Z) / (z − P)

realized as the one-line recursion y[k] = P·y[k−1] + u[k] − Z·u[k−1]. Numerator and denominator are both monic, so the instantaneous gain is 1 and the DC gain is H(1) = (1 − Z) / (1 − P). Which of lead and lag you get follows from the pair rather than from a mode setting: Z > P leads (phase advance, DC gain below one), Z < P lags.

Before the first sample there is neither a previous output nor a previous input, so the two configured initial conditions stand in for them.

Ports

• Input – the signal u to compensate, of any size [p,m].
• Output – the compensated signal y, the SAME size [p,m] as the input.

The compensator is scalar, but it is applied independently to every entry of the input signal, each entry carrying its own memory.

Parameters

• Pole (in Z Plane) – a scalar P, the denominator's root. Defaults to 0.95, Simulink's own default. |P| < 1 is stable, and the closer to 1 the longer the compensator's memory. Any real value is accepted here, but see the Simulink bridge below before using one outside 0 < P < 1.
• Zero (in Z Plane) – a scalar Z, the numerator's root. Defaults to 0.75. Setting Z equal to P cancels the pole and leaves a plain wire, which is accepted rather than rejected – it is a legitimate way to switch a compensator out of a loop. As with the pole, any real value runs here; 0 < Z ≤ 1 is what crosses to Simulink.
• Initial Condition (Previous Output) – a scalar standing in for y[−1] on the first sample, broadcast to every entry. Defaults to 0.
• Initial Condition (Previous Input) – a scalar standing in for u[−1] on the first sample, broadcast to every entry. Defaults to 0.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, all from the shared realization every linear Control Systems / Discrete block uses. The pole, the zero and both initial conditions are baked into the generated core at export time rather than exposed as tunable parameters: the singularities are folded into the A/B/C/D coefficients, and the two initial conditions are combined into the single state seed P·y[−1] − Z·u[−1] that a first-order section actually needs.

Simulink bridge

Import and export, mapped to simulink/Discrete/Transfer Fcn Lead or Lag. "Pole (in Z Plane)" to PoleZ, "Zero (in Z Plane)" to ZeroZ, "Initial Condition (Previous Output)" to ICPrevOutput, "Initial Condition (Previous Input)" to ICPrevInput. All four cross as plain numbers, so the mapping is lossless in either direction.

Simulink restricts the pole and the zero; this block does not. Its block is masked, and the mask rejects anything outside 0 < P < 1 and 0 < Z ≤ 1 – "Pole position must be a positive number less than 1", "Zero position must be a positive number less than or equal to 1". So a compensator configured here with a negative or unstable singularity is perfectly valid in ICore and simulates and exports normally, but the generated Simulink script will stop on it rather than build a block that behaves differently. Keep both inside that box if the model has to cross. The two initial conditions carry no such restriction, and either may be negative.

"Sampling Time (s)" does not cross, unusually: Simulink's block is a masked subsystem with no SampleTime parameter at all, so the rate stays on the ICore side and a block configured with an explicit positive rate reports that it did not carry over. In Simulink it simply inherits the rate of whatever drives it.

Simulink's RndMeth and DoSatur are left at their defaults and have no ICore counterpart: they select a rounding mode and an overflow policy that only bite on fixed-point or integer signals, and ICore's signal path is double precision throughout.

Notes

• Discrete only, and stateful: one state per entry, not two. The block has to remember two past values but only one number – the part of y[k] this step's input does not supply – which is what keeps the realization the same order as the transfer function.
• Being linear, the block is directly usable by the model reduction and linear-analysis commands.
• Lead or Lag vs. First Order. Transfer Fcn First Order is this block with the zero at the origin and the gain normalized to H(1) = 1. Reach for it when all you want is a lag with unity DC gain; reach for this one when the numerator needs a zero of its own.