Tapped Delay — Control Systems/Discrete

Tapped Delay

Control Systems / Discrete

Remembers the last N samples of its input and emits all of them at once as a single column signal – a delay line with every tap brought out:

y[k] = [ u[k−N]   …   u[k−1] ]

That column is the regressor an FIR filter, a correlator or a least-squares identification scheme wants, so one block replaces a ladder of Unit Delays and a Mux. Samples from before the run starts read the configured Initial Condition.

Ports

• Input – the signal u to tap. It must be a scalar [1,1]: the taps are stacked into the output column, so a non-scalar input would need a second dimension the signal type has no room for.
• Output – the tap column, [T,1], where T is Number of Delays, plus one when Include Current Input is on. The size therefore follows the parameters rather than the input.

Parameters

• Number of Delays – N, how many past samples are kept, at least 1. Defaults to 4. It sets the output height.
• Initial Condition – a scalar, the value every tap reads before that sample has been taken. Defaults to 0, and seeds the whole line.
• Delay Order – which end of the line comes first:
  • Oldest (default) – row 1 is the OLDEST sample u[k−N] and the last row is u[k−1].
  • Newest – row 1 is the most recent sample u[k−1] and the last row is u[k−N].
• Include Current Input – whether the undelayed sample u[k] joins the column, which makes the output one row taller:
  • off (default) – only delayed samples; the block has no direct feedthrough.
  • on – u[k] is appended at the END under Oldest and prepended at the FRONT under Newest, so it always sits at the "newest" end of whichever order is in force. The block then has direct feedthrough.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is the spacing between taps, so it is part of the arithmetic and not merely a schedule.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The tap ORDER is resolved at export time into a straight-line assignment per output row – there is no ordering branch left in the generated core – and the line itself is a shift register of N elements seeded with the initial condition. On the three HDL targets the shift is a register-to-register move, which is what a tapped delay is in hardware anyway.

Simulink bridge

Import and export, mapped to simulink/Discrete/Tapped Delay. "Number of Delays" to NumDelays, "Initial Condition" to vinit, "Delay Order" to DelayOrder and "Include Current Input" to includeCurrent; all four values are 1:1, so the mapping is lossless in both directions.

The rate crosses as samptime, not SampleTime. Simulink's Tapped Delay is a masked S-Function and names its rate parameter differently from the rest of the library; emitting the usual name would be a hard set_param error that aborts the whole generated script, so the entry names the parameter it actually has.

Notes

• Stateful: a shift register of N past samples.
• Discrete by nature – the line advances one slot per sample.
• Direct feedthrough only with the current input included. With it off, every output row is a past sample, so the block breaks an algebraic loop exactly as Unit Delay does; with it on, row 1 (or the last row) is the live input and it does not.
• Deliberately carries no state space. A pure delay is the transcendental factor e^(−sT_s), which no finite continuous A/B/C/D expresses; the block runs its discrete shift directly instead.