Memory — Control Systems/Discrete

Memory

Control Systems / Discrete

Holds its input for one step and emits it on the next:

y[k] = u[k−1]

Before the first step has been taken there is no previous input, so the block emits the configured Initial Condition instead. Its usual job is to break an algebraic loop – a feedback path with no storage in it, which the solver cannot resolve – by putting exactly one step of delay in the way.

Ports

• Input – the signal u to hold, of any size [m,n]. Every entry is held independently; the entries do not interact.
• Output – the held signal y, the SAME size [m,n] as the input.

Parameters

• Initial Condition – a scalar, what the block emits on the first step, before any input has been stored. Defaults to 0. It is broadcast to every entry of the signal, so one value seeds a matrix signal whatever its size.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. Note that this one does not cross to Simulink – see the bridge section below.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each carries one held matrix as its state, seeded with the initial condition, which is baked into the core at export time rather than exposed as a tunable parameter – it seeds a state rather than scaling arithmetic.

The three HDL targets need no special handling: the state write is a registered assignment, so reading the state signal within the same tick returns its pre-clock contents – exactly the previous sample. The delay falls out of the register rather than having to be arranged around it.

Simulink bridge

Import and export, mapped to simulink/Discrete/Memory. "Initial Condition" to InitialCondition, and InheritSampleTime is always emitted as off – this block always holds for one step of its own rate, so there is no choice to offer behind that parameter.

"Sampling Time (s)" does not cross. Simulink's Memory block defines no SampleTime parameter at all, unlike almost every other block in the library, so the pair that is mapped globally is suppressed for this entry. That is not a simplification: set_param on a parameter a block does not define is a hard error in MATLAB that aborts the whole generated script, so emitting it would break the export rather than degrade it. The rate stays on the ICore side, and a block configured with an explicit positive rate reports that it did not cross.

Notes

• Stateful: one held matrix, the input from the previous step.
• Discrete by nature – the state advances once per step, so the block is never pushed through a continuous solver's stages.
• Memory vs. Unit Delay. Both compute y[k] = u[k−1] and the arithmetic is identical; the difference is the RATE. Unit Delay delays by its own configured "Sampling Time (s)" and crosses that period to Simulink; Memory delays by one step of whatever drives it and carries no rate across at all. Reach for Unit Delay when the delay length is something you want to state, and for Memory when you just need a break in an algebraic loop at whatever rate the surrounding model happens to run.
• Deliberately carries no state space. A pure delay is the transcendental factor e^(−sT), which no finite continuous A/B/C/D expresses, so fabricating one would let the model-reduction commands absorb a delay into a plant as though it were a gain. The block runs its discrete realization – A=[0], B=[1], C=[1], D=[0] – directly, which also keeps it able to carry the matrix signals an ICoreStateSpace column vector could not.