Fixed Point State Space — Control Systems/Discrete
Control_Systems/Discrete/Fixed_Point_State_Space · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Fixed-Point State-Space
Control Systems / Discrete
A MIMO discrete-time linear system whose matrices are given already discrete – there is no continuous original behind them:
y[k] = C·x[k] + D·u[k]
x[k+1] = A·x[k] + B·u[k]
with n states, m inputs and p outputs, so A is [n,n], B is [n,m], C is [p,n] and D is [p,m]. The output is taken from the state before the update, so the block has direct feedthrough only through D.
Ports
- Input – the input vector u, [m,1], sized from the column count of B and D. The block is genuinely MIMO: the vector is the signal, and the system is not replicated per entry.
- Output – the output vector y, [p,1], sized from the row count of C.
Parameters
- A – the [n,n] discrete state matrix. Its eigenvalues are z-plane poles: the system is stable when all of them lie inside the unit circle.
- B – the [n,m] input matrix; its column count sets the input port width.
- C – the [p,n] output matrix; its row count sets the output port width.
- D – the [p,m] direct feedthrough matrix.
- Initial Condition – the state at the start of the run. A scalar seeds every state with that value (Simulink's default form); an [n,1] vector seeds them individually.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Nothing is discretized on the way out – the matrices are already discrete, so every target realizes the very recursion the simulation runs. A, B, C and D are baked into the generated body as constants rather than exposed as tunable parameters, because changing their dimensions would change the size of the state array the core declares. The three HDL targets carry the recursion in Q16.16 fixed point, like every other discrete block here.
Simulink bridge
Import and export, mapped to simulink/Additional Math & Discrete/
Additional Discrete/Fixed-Point State-Space. "A", "B", "C" and "D" to
A, B, C, D, and "Initial
Condition" to InitialCondition, all as plain pass-through values,
so the round trip is lossless.
The Simulink block's fixed-point machinery has no ICore choice behind it and
is always written out fixed: InternalDataType as
fixdt('double'), which is what makes Simulink's arithmetic double
precision and therefore comparable with ICore's at all;
StateEqScaling and OutputEqScaling as 2^0, and
LockScale off, RndMeth Floor,
DoSatur off – every one of which acts on a fixed-point
stored type that a double-precision block does not have. "Sampling Time (s)"
does NOT cross: this Simulink block defines no SampleTime
parameter at all, so the rate stays on the ICore side and a block given an
explicit period reports that it did not cross.
Notes
- Discrete only, and stateful: the state is the [n,1] vector x.
- No continuous state space is carried, because the matrices are z-domain and there is nothing to recover one from. The model-reduction commands therefore report the block as unmergeable, which is the honest answer – use Discrete State Space when the system does have a continuous original to state.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Fixed_Point_State_Space |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Fixed_Point_State_Space |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Fixed_Point_State_Space/ICoreBlock_0_Control_Systems_1_Discrete_2_Fixed_Point_State_Space.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Fixed_Point_State_Space/ICoreBlock_0_Control_Systems_1_Discrete_2_Fixed_Point_State_Space.h |
| default size on canvas | 130 × 90 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
A | [2.6020 -2.2793 0.6708; 1 0 0; 0 1 0] | A |
B | [1; 0; 0] | B |
C | [0.0184 0.0024 0.0055] | C |
D | [0.0033] | D |
Initial Condition | 0 | InitialCondition |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Additional Math & Discrete/Additional Discrete/Fixed-Point State-Space |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | InternalDataType = fixdt('double'), StateEqScaling = 2^0, OutputEqScaling = 2^0, LockScale = off, RndMeth = Floor, DoSatur = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
A | A | passes through |
B | B | passes through |
C | C | passes through |
D | D | passes through |
Initial Condition | InitialCondition | passes through |
Caveat (shown to the user): the block runs at the surrounding Simulink rate; "Sampling Time (s)" does not cross, because this Simulink block defines no SampleTime parameter
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Fixed-Point State-Space block — MIMO discrete state space, matrices given already discrete y[k] = C x[k] + D u[k] (output from the CURRENT state) x[k+1] = A x[k] + B u[k] (state update, using that same x[k])
Simulation and every one of the ten exports realize that identical recursion; nothing is discretized on the way out, because there is no continuous original to discretize.
The generators read A/B/C/D from CONFIG rather than from getStateSpace_disc(): the model build calls discretizeModel() after the port-sizing pass, which rewrites stateSpace_disc from the (deliberately absent) continuous state space, and the export path never re-runs loadBlockConfig to put it back. Reading config is exact and immune to that ordering.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -0.03635 … 0.3234 |
ramp | Ramp: slope 1 from t = 0 | 0 … 19.4 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -2.838 … 2.83 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -0.7287 … 1.81 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Fixed_Point_State_Space.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).