Discrete Transfer Function — Control Systems/Discrete
Control_Systems/Discrete/Discrete_Transfer_Function · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Discrete Transfer Function
Control Systems / Discrete
A discrete-time SISO transfer function in the shift variable:
H(z) = N(z) / D(z)
realized as the direct-form difference equation y[k] = ∑ numi·u[k−i] − ∑ deni·y[k−1−i]. The coefficients it runs can be typed in directly, or derived by discretizing a continuous N(s)/D(s) you supply.
Ports
- Input – the signal to filter, of any size [p,m].
- Output – the filtered signal, of the same size.
The function is SISO, but it is applied independently to every entry of the input signal, each entry carrying its own history.
Parameters
- Discretization Method – decides which coefficients run: Same as Global Solver discretizes the continuous pair with the model's solver method; Manually Load Discrete Parameters uses the discrete pair as typed; the named methods (Zero-order Hold, First-order Hold, Impulse, Tustin, Matched, Backward Euler, Forward Euler) discretize with that method regardless of the solver.
- Numerator / Denominator - Continues – N(s) and D(s) in descending powers of s, used by every method except direct load.
- Numerator / Denominator - Discrete – N(z) and D(z) in descending powers of z, used only by direct load.
- Initial States – where the filter starts, instead of at rest.
0 (the default) starts it at rest, and a single scalar seeds every state
with that value. A vector gives one value per state, newest first, and
must be as long as the order of the denominator – a row or a column,
whichever you have.
These are the same states Simulink's Discrete Transfer Fcn calls Initial states, and they mean the same thing: the block reproduces Simulink's response from the same seed, sample for sample. That equivalence is measured, not assumed – the numbers are pinned in theinitialstatespre-release suite. It is worth stating because an initial state belongs to a realization rather than to a transfer function: this block runs the direct-form I recursion above, holding past inputs and past outputs, while Simulink's runs direct form II. The two hold different quantities, and the block converts between them for you. - Sampling Time (s) – the update period, and the step the discretization is performed at. Zero or less inherits the solver's rate.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every one emits the same normalized difference equation the in-app run uses, with whichever coefficients the discretization method selects.
Simulink bridge
Import and export, mapped to
simulink/Discrete/Discrete Transfer Fcn.
"Numerator - Discrete" to Numerator, "Denominator - Discrete" to
Denominator, "Initial States" to InitialStates,
"Sampling Time (s)" to SampleTime.
Only the discrete coefficients cross. The continuous pair and the
discretization method are an ICore-side workflow that produces them, and
Simulink's block holds only the result – so they are deliberately left
behind rather than reported as unmapped.
Notes
- Discrete only, and stateful: as many past samples per entry as the denominator's order.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Discrete_Transfer_Function |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Transfer_Function |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_Transfer_Function/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Transfer_Function.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_Transfer_Function/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Transfer_Function.h |
| default size on canvas | 130 × 90 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Discretization Method | Same as Global Solver%~%Manually Load Discrete Parameters… | not crossed |
Numerator - Continues | [1] | not crossed |
Denominator - Continues | [1 2 1] | not crossed |
Numerator - Discrete | [1] | Numerator |
Denominator - Discrete | [1 0.2 0.1] | Denominator |
Initial States | 0 | InitialStates |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discrete/Discrete Transfer Fcn |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| deliberately not crossed | Numerator - Continues, Denominator - Continues, Discretization Method |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Numerator - Discrete | Numerator | passes through |
Denominator - Discrete | Denominator | passes through |
Initial States | InitialStates | passes through |
Caveat (shown to the user): only the discrete numerator/denominator cross to Simulink
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
⚠ Mismatch. Fixed at the source — the description or the code, whichever is wrong (R-D9) — never explained away on a docs page:
B5config variable 'Numerator - Continues' is not documented under ParametersB5config variable 'Numerator - Discrete' is not documented under Parameters
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Discrete Transfer Function block — element-wise (non-scalar) handling The block defines ONE SISO discrete transfer function (num/den), but the input port may carry a [p,m] matrix signal. The same transfer function is applied INDEPENDENTLY to each of the K = p*m entries, and the output is a [p,m] matrix of the per-entry results. There is no cross-coupling between entries — entry e of the input maps only to entry e of the output.
Simulation (compute_h_discrete) One ICoreIIREmulator per input entry: iirEmulators holds K emulators, (re)built in loadBlockConfig from the (already-discretized) transfer function and the live input size. Each step flattens the [p,m] input, runs emulator e on entry e, and reshapes the K results back to [p,m]. The IIR state lives inside the emulators, so compute_f_discrete just returns x untouched — there is no [n,K] block-state to size (and hence none of the continuous block's state-reset gotcha applies here).
Code export (Python/MATLAB/Java/Rust/C/C++ and HDL/PLC) Every generator realizes the SAME direct-form IIR difference equation, with per-entry history buffers, looping over the output port's [p,m] dimensions so each entry gets its own u/y history. Coefficients come from computeNormalizedIIR(), which reads getStateSpace_disc() DIRECTLY (the discrete SS is set per the block's Discretization Method in loadBlockConfig); unlike the continuous TF block, it must NOT call discretize(). See per-language sections below.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -0.2 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 4.331 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.7739 … 0.7749 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2.689 … 2.557 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Discrete_Transfer_Function.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).