Discrete State Space — Control Systems/Discrete
Control_Systems/Discrete/Discrete_State_Space · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Discrete State Space
Control Systems / Discrete
A discrete-time linear system, updated once per sample:
x[k+1] = A·x[k] + B·u[k]
y[k] = C·x[k] + D·u[k]
The matrices it runs can be typed in directly, or derived for you by discretizing a continuous system you supply.
Ports
- Input – the input vector u, [m,1].
- Output – the output vector y, [p,1], sized from the C that is in force.
Parameters
- Discretization Method – decides which set of matrices runs:
- Same as Global Solver – the continuous A/B/C/D are discretized using the model's solver method.
- Manually Load Discrete Parameters – the discrete A/B/C/D are used exactly as typed, and the continuous ones are ignored.
- Zero-order Hold, First-order Hold, Impulse, Tustin, Matched, Backward Euler, Forward Euler – discretize the continuous matrices by that method, whatever the global solver uses.
- A/B/C/D - Continues – the continuous system, used by every method except direct load.
- A/B/C/D - Discrete – the discrete system, used only by direct load.
- Initial State Vector – x at the start of the run, [n,1].
- Sampling Time (s) – the update period, and the step the discretization is performed at. Zero or less inherits the solver's rate.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Whichever matrices the discretization method selects are the ones baked into the generated recursion.
Simulink bridge
Import and export, mapped to simulink/Discrete/Discrete State-Space.
"A/B/C/D - Discrete" to A, B, C,
D; "Initial State Vector" to X0; "Sampling Time (s)"
to SampleTime. Only the discrete matrices cross. The
continuous set and the discretization method are an ICore-side workflow that
produces them, and Simulink's block holds only the result – so they
are deliberately left behind rather than reported as unmapped.
Notes
- Discrete only: the block never integrates, it steps.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Discrete_State_Space |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_State_Space |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_State_Space/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_State_Space.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_State_Space/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_State_Space.h |
| default size on canvas | 130 × 90 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Discretization Method | Same as Global Solver%~%Manually Load Discrete Parameters… | not crossed |
A - Continues | [0 1;-1 -1] | not crossed |
B - Continues | [0; 1] | not crossed |
C - Continues | [1 0] | not crossed |
D - Continues | [0] | not crossed |
A - Discrete | [0 1;-0.1 -0.1] | A |
B - Discrete | [0; 0.1] | B |
C - Discrete | [1 0] | C |
D - Discrete | [0] | D |
Initial State Vector | [0; 0] | X0 |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discrete/Discrete State-Space |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| deliberately not crossed | A - Continues, B - Continues, C - Continues, D - Continues, Discretization Method |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
A - Discrete | A | passes through |
B - Discrete | B | passes through |
C - Discrete | C | passes through |
D - Discrete | D | passes through |
Initial State Vector | X0 | passes through |
Caveat (shown to the user): only the discrete A/B/C/D cross to Simulink
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
⚠ Mismatch. Fixed at the source — the description or the code, whichever is wrong (R-D9) — never explained away on a docs page:
B5config variable 'A - Continues' is not documented under ParametersB5config variable 'B - Continues' is not documented under ParametersB5config variable 'C - Continues' is not documented under ParametersB5config variable 'A - Discrete' is not documented under ParametersB5config variable 'B - Discrete' is not documented under ParametersB5config variable 'C - Discrete' is not documented under Parameters
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Discrete State Space block — MIMO realization A linear MIMO system x[k+1] = A x + B u, y = C x + D u (A:[n,n] B:[n,m] C:[p,n] D:[p,m]). The input port is the [m,1] input vector u, the output port the [p,1] output vector y, and the block state is the [n,1] vector x (the vector IS the MIMO signal — no per-entry concept).
Simulation: compute_f/h_discrete run the recursion on the discrete SS. The discrete SS is set in loadBlockConfig per the block's Discretization Method (same as global / loaded directly / discretized here). Initial state comes from the "Initial State Vector" config.
Code export (Python/MATLAB/Java/Rust/C/C++ and HDL/PLC) Every generator realizes the discrete state-space recursion directly — structurally identical to the in-app simulation: y[k] = C x[k] + D u[k] (output from the CURRENT state) x[k+1] = A x[k] + B u[k] (state update) A,B,C,D are embedded as constants (B=Bu, D=Du to match the simulation), x is the only persistent state, seeded with the configured initial state. ssDiscreteExport() reads getStateSpace_disc() DIRECTLY (configured per method in loadBlockConfig) — unlike the continuous block, no discretize().
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -0.008902 … 0.05456 |
ramp | Ramp: slope 1 from t = 0 | 0 … 4.796 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.3034 … 0.4961 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -0.118 … 0.4753 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Discrete_State_Space.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).