Discrete Derivative — Control Systems/Discrete
Control_Systems/Discrete/Discrete_Derivative · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Discrete Derivative
Control Systems / Discrete
A discrete approximation to the derivative – the change in the input per second rather than per sample:
y[k] = K·(u[k] − u[k−1]) / Ts
Ts is the block's own sampling period, so the block genuinely estimates du/dt. On the very first sample there is no previous input, and the configured initial condition stands in for the weighted term instead. In transfer-function terms it is K(1 − z−1) / Ts.
Differencing amplifies noise: the gain rises with frequency without limit, so a noisy input produces a much noisier derivative. Where that matters, a filtered derivative – the D branch of Discrete PID Controller – is the better instrument.
Ports
- Input – the signal to differentiate, of any size [p,m].
- Output – its estimated rate of change, of the same size.
The derivative is scalar, but it is applied independently to every entry of the input signal, each entry remembering its own previous weighted value.
Parameters
- Gain Value (K) – a scalar multiplying the whole difference quotient. One leaves the plain rate of change.
- Initial Condition (Previous Scaled Input) – the value standing in for K·u[−1]/Ts on the first sample, a scalar applied to every entry. Note it is the weighted term, already carrying the K/Ts factor – not the previous raw input.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is not merely a schedule here: it is the Ts the difference is divided by, so changing it changes the output.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. K and Ts are folded into the single K/Ts coefficient at export time rather than exposed as tunable parameters, so retuning either one means exporting again.
Simulink bridge
Import and export, mapped to
simulink/Discrete/Discrete Derivative.
"Gain Value (K)" to gainval, "Initial Condition (Previous Scaled
Input)" to ICPrevScaledInput.
"Sampling Time (s)" does not cross, unusually: Simulink's Discrete
Derivative is a masked subsystem with no SampleTime parameter
at all, so the rate stays on the ICore side and a block configured with an explicit
positive rate reports that it did not carry over. Since Ts scales the
output here, an exported model whose Simulink rate differs from the ICore one will
not merely be scheduled differently – it will compute a different signal. Set
the two to match deliberately.
Notes
- Discrete only, and stateful: one past weighted sample per entry.
- Being linear, the block is directly usable by the model reduction and linear-analysis commands.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Discrete_Derivative |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Derivative |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_Derivative/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Derivative.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_Derivative/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Derivative.h |
| default size on canvas | 120 × 80 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Gain Value (K) | 1 | gainval |
Initial Condition (Previous Scaled Input) | 0 | ICPrevScaledInput |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discrete/Discrete Derivative |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Gain Value (K) | gainval | passes through |
Initial Condition (Previous Scaled Input) | ICPrevScaledInput | passes through |
Caveat (shown to the user): the sampling time does not cross: Simulink's Discrete Derivative is a masked subsystem with no SampleTime parameter, and inherits the rate of whatever drives it - which matters more here than usual, because Ts divides the output rather than only scheduling it
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Discrete Derivative block — y[k] = K*(u[k] - u[k-1])/Ts, element-wise The one state is the previous WEIGHTED input K*u[k-1]/Ts, which is what Simulink's initial condition names, so it carries over without rescaling. See the header for the A/B/C/D. Everything below the matrices comes from ICoreDiscreteLinearBlockBase.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -10 … 10 |
ramp | Ramp: slope 1 from t = 0 | 0 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1.995 … 1.996 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -50 … 10 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Discrete_Derivative.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).