Wrap To Zero — Control Systems/Discontinuities
Control_Systems/Discontinuities/Wrap_To_Zero · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Wrap To Zero
Control Systems / Discontinuities
Passes the input straight through while it stays at or below a threshold, and outputs zero the moment it goes above: y = u when u ≤ threshold, y = 0 when u > threshold. Applied entry by entry, so a matrix signal is treated element for element.
Ports
- Input – the signal u, of any size [m,n].
- Output – y, of the SAME size [m,n]. The block never reshapes a signal.
Parameters
- Threshold – scalar. Defaults to 255, as in Simulink – the block's usual job is wrapping a counter that has run past its range.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
The threshold is a scalar; a per-entry threshold sized like the input is not implemented and is reported rather than broadcast from its first entry.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The threshold is baked into the generated code as a constant at export time rather than exposed as a tunable parameter, matching the other Discontinuities blocks.
Simulink bridge
Import and export, mapped to simulink/Discontinuities/Wrap To Zero.
"Threshold" to Threshold as a plain pass-through value, so the
round trip is lossless. "Sampling Time (s)" goes to SampleTime, as
on every block.
Notes
- Algebraic, with no state.
- The comparison is one-sided: only the UPPER side wraps. A large negative input passes through unchanged.
- Not linear, and so deliberately carries no state space – model reduction reports it as unmergeable rather than absorbing the step to zero.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discontinuities/Wrap_To_Zero |
| family | Control_Systems/Discontinuities |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discontinuities_2_Wrap_To_Zero |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Wrap_To_Zero/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Wrap_To_Zero.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Wrap_To_Zero/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Wrap_To_Zero.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Threshold | 255 | Threshold |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discontinuities/Wrap To Zero |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Threshold | Threshold | passes through |
Caveat (shown to the user): the block runs at the surrounding Simulink rate; "Sampling Time (s)" does not cross
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Wrap To Zero block — pass through up to a threshold, then drop to zero y = u when u <= threshold, y = 0 when u > threshold. Applied INDEPENDENTLY to every entry of the input signal, so the output keeps the input's size. Algebraic and stateless, and deliberately carries no state space (see the header).
Code export: the threshold is inlined as an export-time constant, per language.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -2 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | -2 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | -2 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | -2 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | -2 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | -2 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | -2 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discontinuities__Wrap_To_Zero.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).