Saturation — Control Systems/Discontinuities
Control_Systems/Discontinuities/Saturation · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Saturation
Control Systems / Discontinuities
Holds the input inside a band: y = min(max(u, lower), upper). Values above the upper limit come out AS the upper limit, values below the lower limit as the lower limit, and everything between passes through unchanged. The clamp is applied entry by entry, so a matrix signal is saturated element for element.
Ports
- Input – the signal u to clamp, of any size [m,n].
- Output – the clamped signal y, of the SAME size [m,n]. The block never reshapes a signal.
Parameters
- Upper Limit – scalar, the top of the band. Defaults to 0.5, as in Simulink.
- Lower Limit – scalar, the bottom of the band. Defaults to -0.5, as in Simulink. It must not exceed the upper limit; an inverted band is reported and the run is stopped rather than silently producing a constant.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Both limits are scalars. Simulink additionally accepts a limit sized like the input, for a per-entry band; that form is not implemented here and is reported rather than broadcast from its first entry.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. Each target uses its own idiomatic clamp
(np.clip, min/max,
f64::clamp, fmin/fmax, an
if/elsif chain in the HDLs,
MIN/MAX in ST). The two limits are baked into the
generated code as constants at export time rather than exposed as tunable
parameters – the same choice the Integrator makes for its identical
limiting pair.
Simulink bridge
Import and export, mapped to simulink/Discontinuities/Saturation.
"Upper Limit" to UpperLimit and "Lower Limit" to
LowerLimit, both as plain pass-through values, so the round trip is
lossless. "Sampling Time (s)" goes to SampleTime, as on every
block.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear, and so deliberately carries no state space. Model reduction reports it as unmergeable instead of absorbing it into a neighbouring plant – which would quietly discard the very nonlinearity the block exists to introduce.
- The band is closed: an input exactly ON a limit passes through as that limit.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discontinuities/Saturation |
| family | Control_Systems/Discontinuities |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discontinuities_2_Saturation |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Saturation/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Saturation.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Saturation/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Saturation.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Upper Limit | 0.5 | UpperLimit |
Lower Limit | -0.5 | LowerLimit |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discontinuities/Saturation |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Upper Limit | UpperLimit | passes through |
Lower Limit | LowerLimit | passes through |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Saturation block — per-entry clamp into [Lower Limit, Upper Limit] y = min(max(u, lower), upper), applied INDEPENDENTLY to every entry of the input signal. The output port carries the input's size. Algebraic and stateless.
Deliberately carries NO state space: the block is linear only strictly inside the band, so no A/B/C/D can express the flat regions, and letting model reduction merge it would delete the nonlinearity. See the header for the full reasoning.
Code export: the two limits are inlined as export-time constants, per language, using the same clamp idiom the Integrator's output limiting already uses in each target.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -0.5 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | -0.5 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | -0.5 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | -0.5 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | -0.5 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | -0.5 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | -0.5 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0.5 |
ramp | Ramp: slope 1 from t = 0 | 0 … 0.5 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.5 … 0.5 |
step | Step: 0 -> 1 at t = 1 s | 0 … 0.5 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discontinuities__Saturation.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).