Relay — Control Systems/Discontinuities
Control_Systems/Discontinuities/Relay · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Relay
Control Systems / Discontinuities
Switches between two output levels with hysteresis. The output goes to its on level once the input reaches the switch-on point, drops to its off level once the input falls to the switch-off point, and holds whatever it last was anywhere in between. That hold band is the whole point: a single threshold would chatter on a noisy signal, a relay will not. Applied entry by entry.
Ports
- Input – the signal u, of any size [m,n].
- Output – y, of the SAME size [m,n], always equal to either the on level or the off level. The block never reshapes a signal.
Parameters
- Switch On Point – scalar. At or above it the output latches on. Defaults to eps (2.2204e-16), as in Simulink.
- Switch Off Point – scalar. At or below it the output latches off. Defaults to eps. It must not exceed the switch-on point; the two being equal is legal and simply removes the hysteresis.
- Output When On – the on level. Defaults to 1.
- Output When Off – the off level. Defaults to 0.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
All four are scalars; per-entry vectors are not implemented and are reported rather than broadcast from their first entry.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. All four parameters are baked in as constants at export time. The exported state is the latched output itself, one value per entry, seeded with the off level – so a generated core starts off, just like the in-app block, and every target's step reads decide → write → store.
Simulink bridge
Import and export, mapped to simulink/Discontinuities/Relay.
"Switch On Point" to OnSwitchValue, "Switch Off Point" to
OffSwitchValue, "Output When On" to OnOutputValue,
"Output When Off" to OffOutputValue, all as plain pass-through
values, so the round trip is lossless. "Sampling Time (s)" goes to
SampleTime, as on every block.
Notes
- Stateful: one latched output per input entry. It starts at the off level, so a relay whose input begins inside the hold band outputs the off level until the input first reaches the switch-on point.
- Both comparisons are inclusive: an input exactly ON a switch point takes that action.
- Not linear, and so deliberately carries no state space.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discontinuities/Relay |
| family | Control_Systems/Discontinuities |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discontinuities_2_Relay |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Relay/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Relay.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Relay/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Relay.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Switch On Point | 2.220446049250313e-16 | OnSwitchValue |
Switch Off Point | 2.220446049250313e-16 | OffSwitchValue |
Output When On | 1 | OnOutputValue |
Output When Off | 0 | OffOutputValue |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discontinuities/Relay |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Switch On Point | OnSwitchValue | passes through |
Switch Off Point | OffSwitchValue | passes through |
Output When On | OnOutputValue | passes through |
Output When Off | OffOutputValue | passes through |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Relay block — hysteretic on/off switch u >= onPoint -> onOutput; u <= offPoint -> offOutput; in between the output HOLDS. Stateful: the latched output is the state, one entry per input entry, seeded with offOutput so the relay starts off (Simulink's convention). No state space (see header).
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | 0 |
| 0.4 | 0.5 | 1 |
| 0.8 | -2 | 0 |
| 1.2 | 0.5 | 1 |
| 1.6 | -2 | 0 |
| 2 | 0.5 | 1 |
| 2.4 | -2 | 0 |
| 2.8 | 0.5 | 1 |
| 3.2 | -2 | 0 |
| 3.6 | 0.5 | 1 |
| 4 | -2 | 0 |
| 4.4 | 0.5 | 1 |
| 4.8 | -2 | 0 |
| 5.2 | 0.5 | 1 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 1 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discontinuities__Relay.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).