Hit Crossing — Control Systems/Discontinuities

Hit Crossing

Control Systems / Discontinuities

Reports the sample at which the input reaches or crosses an offset. With d = u − offset and d' the previous sample's value of d, the output is 1 on a hit and 0 otherwise:

• d = 0 → hit, in every direction mode – the signal is sitting exactly on the offset.
• rising → hit when d' < 0 and d > 0.
• falling → hit when d' > 0 and d < 0.
• either → hit when d'·d < 0.

A reported hit leaves the block on the offset: d' for the next sample is 0, not the value that carried the signal across. A crossing is therefore reported once, and two hits can never land on consecutive samples – the same rule as "leaving the offset is not a hit" below, applied to every hit rather than only to an exact landing. Under rising and falling this changes nothing (a hit already forces d to the side that forbids an immediate repeat); under either it is the difference between reporting every sign change and reporting every crossing.

Applied entry by entry, so a matrix signal is treated element for element and each entry carries its own history.

Ports

• Input – the watched signal u, of any size [m,n].
• Output – the hit indicator, of the SAME size [m,n], carrying 1 or 0 per entry. The block never reshapes a signal.

Parameters

• Hit Crossing Offset – scalar, the level being watched. Defaults to 0, as in Simulink.
• Hit Crossing Direction – which crossings count:
  • either – any sign change of d. The default.
  • rising – only upward crossings.
  • falling – only downward crossings.
  The d = 0 rule fires in all three, which is the block's own behaviour and not a simplification.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

The offset is a scalar; a per-entry offset sized like the input is not implemented and is reported rather than broadcast from its first entry.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The offset is baked in as a constant at export time, and the direction selects which comparison is emitted rather than being tested at run time, so the generated core carries no mode branch at all. The exported state is the previous value, one per entry – the previous input, or the offset where that sample was a hit – together with the first-sample flag that keeps a run from inventing a crossing before it has any history. Every target writes that state from inside the hit branch, so the generated code cannot report a crossing twice any more than the block can.

Simulink bridge

Import and export, mapped to simulink/Discontinuities/Hit Crossing. "Hit Crossing Offset" to HitCrossingOffset as a plain pass-through value; "Hit Crossing Direction" to HitCrossingDirection through a 1:1 table (either / rising / falling), so the round trip is lossless. The block is always exported showing its output port and emitting a signal rather than a message or function call – ShowOutputPort is fixed to on and HitCrossingOutputType to Signal, because ICore has no counterpart for the other two. "Sampling Time (s)" goes to SampleTime, as on every block.

Notes

• Stateful: one previous value per entry – the previous input, or the offset when that sample was a hit. The first sample has no predecessor, so it can only report a hit through the d = 0 rule.
• Leaving the offset is not a hit: with d' = 0 and d ≠ 0 the block reports 0, having already reported the arrival on the previous sample. Because a hit stores the offset, this covers the sample after every hit, not only the ones that landed exactly on it.
• Discrete by nature – the test compares consecutive samples, so the block always runs at its own rate rather than being pushed through a continuous solver's stages.
• Not linear, and so deliberately carries no state space – the output is a boolean event, which no A/B/C/D can express.