Dead Zone Dynamic — Control Systems/Discontinuities
Control_Systems/Discontinuities/Dead_Zone_Dynamic · 3 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Dead Zone Dynamic
Control Systems / Discontinuities
Produces no response inside a band, exactly like Dead Zone, except that the band arrives on input ports instead of sitting in the configuration: y = u − up above it, y = u − lo below it, and y = 0 inside. Because the edges are signals they may move while the model runs. Applied entry by entry.
Ports
- Input 1 – up – the upper edge of the band.
- Input 2 – u – the signal. Its size is the block's output size.
- Input 3 – lo – the lower edge of the band.
- Output – the dead-zoned signal y, of the SAME size as u.
The port order up, u, lo is Simulink's for this block, top to bottom. All three inputs must carry the same signal size; a mismatch is reported and the run is stopped rather than broadcast.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. ICore-side only – see the bridge note below.
There are no other parameters: everything this block needs comes in on a port.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Nothing is baked in as a constant – all three operands are read from signals every step, so the generated code carries no parameters at all.
Simulink bridge
Import and export, mapped to
simulink/Discontinuities/Dead Zone Dynamic. There are no parameters to
map in either direction; the block's whole configuration is its wiring, and the
up, u, lo port order is what has to line up.
"Sampling Time (s)" does NOT cross: this Simulink block defines no dialog
parameters at all, SampleTime included, so the rate stays on the
ICore side and an explicitly set one is reported rather than written.
Notes
- Algebraic, with no state.
- An inverted band (lo above up) is NOT an error here – the edges are signals, so it can happen for a single step. The arithmetic then follows its own order: the upper test is applied first.
- Not linear, and so deliberately carries no state space.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discontinuities/Dead_Zone_Dynamic |
| family | Control_Systems/Discontinuities |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discontinuities_2_Dead_Zone_Dynamic |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Dead_Zone_Dynamic/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Dead_Zone_Dynamic.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Dead_Zone_Dynamic/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Dead_Zone_Dynamic.h |
| default size on canvas | 120 × 80 px |
| ports at insert | 3 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | up |
| 2 | in | ICoreDouble | u |
| 3 | in | ICoreDouble | lo |
| 4 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discontinuities/Dead Zone Dynamic |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the band arrives on ports (up, u, lo); the Simulink block defines no dialog parameters, so "Sampling Time (s)" does not cross
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Dead Zone Dynamic block — dead zone whose band arrives on signals y = u-up above the band, u-lo below it, 0 inside, entry by entry, with up / u / lo on input ports 0 / 1 / 2 -- Simulink's order for this block. Algebraic and stateless; the output carries port 1's size and all three inputs must agree. No state space (see header).
The Simulink block exposes NO dialog parameters at all -- verified against the R2026a block dialog -- hence an empty params list and hasSampleTimeParam=false.
Sample results#
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|---|---|
| 0 | -2 | -2 | -2 | 0 |
| 0.4 | 0.5 | 0.5 | 0.5 | 0 |
| 0.8 | -2 | -2 | -2 | 0 |
| 1.2 | 0.5 | 0.5 | 0.5 | 0 |
| 1.6 | -2 | -2 | -2 | 0 |
| 2 | 0.5 | 0.5 | 0.5 | 0 |
| 2.4 | -2 | -2 | -2 | 0 |
| 2.8 | 0.5 | 0.5 | 0.5 | 0 |
| 3.2 | -2 | -2 | -2 | 0 |
| 3.6 | 0.5 | 0.5 | 0.5 | 0 |
| 4 | -2 | -2 | -2 | 0 |
| 4.4 | 0.5 | 0.5 | 0.5 | 0 |
| 4.8 | -2 | -2 | -2 | 0 |
| 5.2 | 0.5 | 0.5 | 0.5 | 0 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0 |
ramp | Ramp: slope 1 from t = 0 | 0 … 0 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 0 |
step | Step: 0 -> 1 at t = 1 s | 0 … 0 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discontinuities__Dead_Zone_Dynamic.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).