Lamp — Control Systems/Dashboard
Control_Systems/Dashboard/Lamp · 0 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Lamp (Dashboard)
Control Systems / Dashboard
An indicator that takes its body colour from the value of a signal it is told the name of – without being wired to it. It has no ports at all, and nothing on its face: a lamp is its colour.
Ports
- None. Not one input, not one output. That is what makes it a dashboard block.
Naming the signal to watch
ICore links carry names, and that name is the selection: rename a link (its
name is editable like a block's) and put that name here. A name containing
/ is matched against the link's full path instead, which is how two
links called state in different subsystems are told apart. Matching runs
over this block's own subsystem and everything below it, never above – that
is exactly the set of signals a generated core contains.
How the colour is chosen
State Values lists the values that have a colour and State Colors gives one RGB row for each of them, in the same order. The watched value is compared against the list and the FIRST entry it matches wins; a value matching nothing shows Default Color. With the defaults, a signal of 0 is grey and a signal of 1 is green.
⚠ The match is EXACT, and that is Simulink's rule rather than a
simplification of it – its StateColors pairs a colour with a
value, not with a band. So this block is for a signal that takes a few
settled values: a mode, a flag, a fault code. Pointed at a continuous signal it
will sit at Default Color, which is exactly what Simulink's Lamp does. Put
a Compare To Constant or a Quantizer in front of it if what you want
is a threshold.
Only the FIRST element of a matrix signal is read – one lamp shows one state.
Parameters
- Signal – the link name to watch, for example
modeorPlant/fault. Empty watches nothing and the lamp stays at its default colour. This names a link in the diagram, not a variable, so it is never looked up in the variables space. A name that matches no link is reported by name when the run starts. - State Values – the values that have a colour, for example
[0 1]. - State Colors – one RGB row per state value, components 0–255,
for example
[192 192 192; 0 200 0]. It must have exactly as many rows as State Values has entries, and exactly three columns; anything else is reported and stops the run. - Default Color – the RGB shown when the value matches no state.
- Sampling Time (s) – how often the value is read. Zero or less inherits the solver's rate.
Notes
- The colour is one sample behind. Solver order follows input dependencies, and a block with no inputs has none – so this block runs at the head of every step and reads what its source published on the previous one. That is inherent to watching a signal instead of receiving it.
- The lamp keeps the run's final colour after the run ends, rather than reverting – the last state is usually the one worth reading.
- Simulink's Automotive Indicator Lamps, Basic Shape Icons and
Wireless Icons are not separate blocks: all 64 of them report
BlockType=LampBlockand are this block with a different picture.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. A deployable target has no lamp to light, so what
each one emits is the STATE INDEX the lamp would be showing – the 0-based
position in State Values that matched, or -1 for the default
colour. That is the block's whole computation, and it is the half a deployable
target can act on: drive an output, an LED or an alarm from it. PLC Structured
Text emits comments only, naming the signal array entry to tap, since ST has
no console. The one-sample shift above applies to the exported code too, and for
the same reason – so the export agrees with the app.
Code-export verification
This block is excluded from the code-export verification matrix, by
name, in ICoreParityRigLibrary::unriggableTypes(). The verifier
records a terminal block's input signals and compares them; a block with
no inputs records nothing, so a rig around it would fail all ten languages at
residual 0 with "Each matrix must have at least two columns" – a red row
that says nothing about the block. The exclusion is reported by
exportVerify with that reason rather than dropping it silently.
Simulink bridge
None, and that is a measurement rather than a gap. Simulink's
Lamp (BlockType=LampBlock) has ZERO ports of any kind and is
VIRTUAL – measured on R2026a, where a model holding one and nothing else
refuses to run with "contains no blocks or all blocks are virtual". It
reaches its signal through Binding, a canvas selection stored outside
the block's parameters, and ICore has no counterpart for that. This block is the
ICore reading of it – the signal is named rather than clicked – so it
is a DIFFERENT block from the Simulink one rather than a mapping of it, and it is
reported on exchange rather than asserted.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Dashboard/Lamp |
| family | Control_Systems/Dashboard |
| solver environment class | ICoreBlock_0_Control_Systems_1_Dashboard_2_Lamp |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Dashboard/Lamp/ICoreBlock_0_Control_Systems_1_Dashboard_2_Lamp.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Dashboard/Lamp/ICoreBlock_0_Control_Systems_1_Dashboard_2_Lamp.h |
| default size on canvas | 60 × 60 px |
| ports at insert | 0 in, 0 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
The constructor creates no port explicitly — the port list comes from registerInitialPorts (0 in, 0 out) or from the block's configuration.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Signal | — | — |
State Values | [0 1] | — |
State Colors | [192 192 192; 0 200 0] | — |
Default Color | [192 192 192] | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): Simulink's Lamp (BlockType=LampBlock) has ZERO ports of any kind and is VIRTUAL - measured on R2026a, where a model holding one and nothing else refuses to run with "contains no blocks or all blocks are virtual". It does not receive its value on a wire: it reaches the signal through Binding, a canvas selection stored outside the block's parameters, and ICore has no counterpart for that. This block is the ICore reading of that indicator - the signal is named rather than clicked - so it is a DIFFERENT block from the Simulink one rather than a mapping of it, and it is reported on exchange rather than asserted. There is also nothing to compare against: the Simulink block is virtual, so no simulation of it produces a sample. Note that Simulink's Automotive Indicator Lamps, Basic Shape Icons and Wireless Icons are all this same LampBlock with a different picture, not separate blocks
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Dashboard Lamp -- an indicator whose BODY COLOUR is driven by a signal bound by name It has no ports at all. "Signal" names the link to watch; "State Values" lists the values that have a colour and "State Colors" gives one RGB row for each; anything else shows "Default Color". The first matching entry wins.
⚠ THE MATCH IS EXACT, and that is Simulink's rule rather than a simplification of it: its StateColors pairs a colour with a VALUE, not with a band. A Lamp is for signals that take a few settled values -- a mode, a flag, a fault code -- and on a continuous signal it sits at Default Color, which is exactly what Simulink's does.
⚠ THERE IS NO SIMULINK COUNTERPART TO MAP ONTO, AND THAT IS A MEASUREMENT RATHER THAN A GAP. R2026a, measured on 2026-09-17: simulink_hmi_blocks/Lamp reports BlockType=LampBlock, ZERO ports of any kind, NO SampleTime, and a model holding one and nothing else refuses to run -- "contains no blocks or all blocks are virtual". Its signal arrives through Binding, a canvas selection stored outside the block's parameters. So the catalog entry is Support::None with that measurement as its reason, and no parity testbench is owed or possible: a virtual block produces no sample to compare against.
⚠ Simulink's three icon collections -- Automotive Indicator Lamps (34), Basic Shape Icons (24) and Wireless Icons (6) -- are NOT separate blocks. All 64 report BlockType=LampBlock: they are this block with a different picture, and the board records them as such.
The live colour goes through ICoreBlock::setFaceIndicatorColor(), which hops to the GUI thread the way setFaceText() does. setFrameBackgroundColor() would NOT do -- it writes the scene item directly and is constructor-time only.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.